Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

Abstract

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This timeinterleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.

Design of a delayless feedback path free 2nd-order two-path time-interleaved discrete-time delta-sigma modulator- a new approach

“…The "delayless feedback path" problem makes the implementation of multi-path TI ΔΣ modulator impractical [4]. We have developed a new approach to circumvent this problem effectively with reduced complexity and the focus of this paper is on this approach.…”

Design and simulation of a 3rd-order Discrete-Time Time-Interleaved delta-sigma modulator with shared integrators between two paths

“…Equation set (7) can be rewritten as equation set (8): (9) is derived by further substituting equation set (6) into equation set (8). (6) and (9).…”

A 28mW 320MHz 3rd-order continuous-time time-interleaved delta-sigma modulator with 10MHz bandwidth and 12 bits of resolution

“…In DTTI ∆Σ modulator which is shown in Figure 2 and expressed by equation (1.c) in which ( ) (the input of quantizer Q1) is directly linked to ( ). This means that the output of the second quantizer (Q2) is connected to the input of another quantizer (Q1) without any delay [8]. The novel method proposed in this paper resolves this issue and is based on an error correction technique.…”