DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems

Cui, Jinhua; Zhang, Youtao; Wu, Weiguo; Yang, Jun; Wang, Yinfeng; Huang, Jianhang

doi:10.1109/tcad.2017.2766156

Cited by 19 publications

(7 citation statements)

References 29 publications

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“…Unlike Fifer which looks at micro-service chains, Swayam is specifically catered for single-function machine learning inference services. Exploiting Slack: Exploiting slack between tasks is a wellknown technique, which has been applied in various domains of scheduling, including SSD controllers [31,37], memory controllers [41,67,77,89,96], and network-on-chip [32,62,72]. In contrast to exploiting slack, we believe the novelty aspect lies in identifying the slack in relevance to the problem…”

Section: Related Workmentioning

confidence: 99%

Fifer

Gunasekaran

Thinakaran

Nachiappan

et al. 2020

Proceedings of the 21st International Middleware Conference

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Section: Related Workmentioning

confidence: 99%

Fifer

Gunasekaran

Thinakaran

Nachiappan

et al. 2020

Proceedings of the 21st International Middleware Conference

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“…Chen et al [14] established a delay model to dispatch and schedule read/write requests separately according to the obtained delay value. Cui et al [15] proposed to schedule read requests according to retention time and write requests according to hotness, in order to be aware of device process variations. Liu et al [16] pointed that 3D flash memory suffered from reduced utilization of chip-level parallelism when the layer information is added, inducing sub-optimal parallel performance.…”

Section: Introductionmentioning

confidence: 99%

Layer-Aware Request Scheduling for 3D Flash-Based SSDs

Ding

2021

IEEE Access

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Recent development on 3D flash memories largely promotes the wide application of Solid-State Drives (SSDs) by providing larger capacity from vertically-stacked layers. However, there exist speed variations across different layers because of manufacturing process variations or physical designs, which induces new challenges to fully explore the advantages of existing SSDs, e.g. the parallel structure. This paper investigates the effect of speed variation on the parallel performance of SSDs. To balance chips' workloads, traditional method selects chips in a round-robin way. As chip queue time can be estimated by some main factors, the chip also can be chosen in a greedy way. However, because of the layer speed variation, queue time estimation model should be modified. This paper first establishes a new queue time estimation model with the awareness of the flash layer information. Then the model is used to estimate the chip queue time and to direct write requests into the chip with the least queue time. The key idea is to largely reduce queue time of each write, thus reducing the average SSD response time. Finally, this new request redirection method is evaluated on SSDsim with real world workloads. Experimental results show that our model can estimate the queue time more accurately and our new request redirection method can improve 8.3% of write queue time on average under the situation of 4 times speed variation among 16 layers.

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“…We refer to the number of read-retry operation as RL (Read-Level) below. Many research works have devoted to the optimization of large read latency in the aged SSD [11,12,13]. As the NAND flash adjusts the read voltage to sense the electrons in the cell incrementally, these methods proposed to keep track of the last successful RL for the future reads at different granularity(i.e., page-level, block-level, and layer-level).…”

Section: Introductionmentioning

confidence: 99%

Error source and latency-aware read performance optimization scheme for aged SSDs

Nie

Zhang

et al. 2021

IEICE Electron. Express

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LDPC code has been used widely in NAND flash-based storage system due to its high error correction capacity, prolonging the lifetime of multi-bit NAND flash. However, the LDPC decoding latency degrades the read performance of SSD as it induces more read-retry operations. The last RL(Read-Level) recording method has been proposed in recent research works, which achieves better performance improvement by reducing many useless fail reads. However, these schemes reset the RL of these pages to be 1 after these blocks are erased. Using RL 1 to read these pages may induce many fail reads at first read on each page. That because it ignores the different error source issues, i.e., a part of the page error comes from the P/E cycles, while others come from retention time and other sources. Motivated by this observation, in this paper, we propose two schemes to optimize the read procedure of NAND flash-based SSD, especially for aged SSDs. We propose to record RL induced by different error sources separately, so the RL of the page could keep unchanged rather than 1 after the blocks are erased. The scheme could reduces useless fail read after the blocks are read at first time. We also design a latency aware I/O scheduler to reorder the input read requests in batch by prioritizing requests with low latency to reduce the queue latency. Our experiments show that the proposed scheme can reduce the average response time by up to 33% with less storage overhead.

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DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems

Cited by 19 publications

References 29 publications

Fifer

Fifer

Layer-Aware Request Scheduling for 3D Flash-Based SSDs

Error source and latency-aware read performance optimization scheme for aged SSDs

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