Dislocation Generation in Device Fabrication Process

Abstract

In this paper we discuss the physical mechanism and the critical factors for the dislocation generation in device processing. The mechanisms of the stress development are identified. Elastic stress is estimated from the convergent beam electron diffraction (CBED) measurements using transmission electron microscopy (TEM), and the defect generation is monitored by electrical measurements of a specific monitor structure. The implantation conditions and the implantation damage recovery is shown to be another key factor in the defect generation. Thermal oxidations of the STI structure are shown to be a major responsible of the stress increase. In addition to the process the pattern geometry strongly affects the mechanical stress. Minimum geometry structures with a complex layout are prone to defect generation.

Mechanical Stress and Defect Formation in Device Processing

“…After the defect nucleation, the high temperature annealing aimed to the elastic stress release cannot recover the crystal integrity, on the contrary it may result in defect growth. Indeed, Scanning Electron Microscopy (SEM) inspections after selective etching confirmed this interpretation by showing that in the absence of a previous stress release annealing some defects nucleate at step D. Though the effect of amorphizing implantations is usually dominant in defect generation in devices, a role of low dose implantations was previously observed (10,16). In this case, both microscopy and electrical analyses showed that the diode structures (table I) are more prone to generate defects at this level than the transistor array structures (table II).…”

“…3 shows that the depth of the averaging region is very important in determining the computation results. Previous results indicate that defect formation most frequently takes place in the recristallization of highly stressed regions (10,16), so the stress values in the region damaged by the implantation are crucial for defect formation. Therefore we chose to average the stress components over a depth roughly corresponding to the depth of the amorphous region produced by arsenic high dose implantation used for the source and drain formation.…”

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

“…Electrical measurements. Dislocations in transistors are electrically active if they connect the source and the drain regions (8,10,17,21). In this case, the dislocation usually acts as a source-to-drain conductive path, because of the anomalous dopant diffusion from the source and drain regions along the dislocation.…”