DOI: 10.1109/stier.1987.716384
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Abstract: The present study focuses on the realization of the polynomial expression Ax2 + Bx + C. The computation of the polynomial expression is achieved in a parallel and pipelined structure with time and hardware savings if compared to a direct realization of the expression with explicit calculations. The layout of the hardware is simple, given the uniformity of matrices, thus suitable for VLSI design.

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