This paper presents a methodology for testing highperformance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. A clock timing circuit capable of achieving a timing resolution of 50ps in 0.18 m CMOS technology is presented. The design provides the ability to test the clock timing circuit itself.
scite is a Brooklyn-based startup that helps researchers better discover and evaluate scientific articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by researchers from dozens of countries and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.