DOI: 10.1109/date.2003.1253610
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Abstract: This paper presents a methodology for testing highperformance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. A clock timing circuit capable of achieving a timing resolution of 50ps in 0.18 m CMOS technology is presented. The design provides the ability to test the clock timing circuit itself.