Device Quality GaAs Grown at Low Temperature by the Halide Process

Abstract

A study of the parameters which must be controlled to enable the vapor growth of GaAs at low temperature (LT.VPE) using the AsC1JGaAs/H2 system has led to routine growth of MESFET layers at 630~ The source temperature was determined from transport efficiency measurements and set in the range 670~176The growth rate dependence on temperatures and the AsCI~ mole fraction were determined. The morphology of the layer was optimized as a function of the AsCh mole ~raction and the misorientation of the substrate. The best value of misorientation is about 6 ~ off (001). These growth conditions were applied to submicron layer growth, and MESFET devices were fabricated. A comparison of the device performances obtained on layers deposited at high (750~ and low (630~ temperature shows an improvement on unbuffered layers grown at low temperature. Furthermore, the growth of an n-buffer layer at low temperature improves the noise figure still further. Typical results without buffer layers, at 10 GHz, are 4 dB NF, 7.5 dB associated gain, and 11 dB maximum gain.The AsC13/Ga/H2 and AsC1JGaAs/H2 chemical vapor transport systems, first described by Knight et al. ( 1), are widely used for the epitaxial growth of device-quality GaAs. Most of the work is performed using deposition temperatures TD in the range 770 ~ 705~ (2-4), but for several reasons it becomes attractive to lower the source and deposition temperatures (TD < 700~ : Firstly, according to Weiner's calculation ( 5) and Di Lorenzo's data ( 6), silicon contamination is minimized at low temperatures; the second aspect is related to the thermal stability of GaAs (7). This last factor is of particular interest for MESFET devices for which submicron layers are deposited on semi-insulating substrates and whose rf performances and static characteristics are strongly dependent on the material and interface quality (8).Several workers (9, 10) have reported on new methods for low temperature epitaxy (< 700~ but most of their experimental conditions were based on out-of-equilibrium or out-of-steady-state conaitions. Their results suggest that undecomposed AsC13 molecules cause supplementary reactions which allow larger supersaturation.The aim of this work is: first, to define what can be expected for transport conditions in the temperature range 600~176and more particularly at 630~ which is near the congruent evaporation point of GaAs (11); and second, to define an optimum set of conditions for epitaxial growth and to apply it to the MESFET layers.

Chemical Vapor Deposition of TiSi Nanowires on C54 TiSi2 Thin Film: An Amorphous Titanium Silicide Interlayer Assisted Nanowire Growth

“…By reacting TiCl 4 with silane or silicon chlorides at high temperatures, titanium silicide thin films can be grown. 21,[31][32][33] CVD provides possibilities to prepare kinetically stable phases which are difficult to obtain using the other methods. Recently, by employing variations of the fabrication methods mentioned above, preparations of nanosized one-dimensional (1D) silicides of Ti, V, Cr, Mn, Fe, Co, Ni, and Ta have been reported.…”

“…The last one is chemical vapor deposition (CVD) reactions. By reacting TiCl 4 with silane or silicon chlorides at high temperatures, titanium silicide thin films can be grown. ,− CVD provides possibilities to prepare kinetically stable phases which are difficult to obtain using the other methods. Recently, by employing variations of the fabrication methods mentioned above, preparations of nanosized one-dimensional (1D) silicides of Ti, V, Cr, Mn, Fe, Co, Ni, and Ta have been reported. ,,− For titanium silicides, these include nanowires (NWs) of TiSi and C54-TiSi 2 , nanopins (NPs) of TiSi, nanobats of Ti 5 Si 4 , and nanonets (NNs) of C49-TiSi 2 , as listed in Table . ,,,,, Previously, we have communicated the growth of Ti 5 Si 3 NWs on top of C54-TiSi 2 thin films grown by reacting titanium subhalides TiCl x (g) , generated by passing TiCl 4(g) over Ti (s) at 1173 K, with Si substrates in a CVD process .…”

Deep Level Study of VPE Layers for GaAs FET Devices

“…However, with the availability of high purity GaAs material in recent years, AsC1jH2/GaAs solid Source method can be considered seriously as an alternative to produce VPE layers. Recent results have indicated that device quality epitaxial layers, grown with solid GaAs source, with background doping in the mid 10 ls cm -3 range and Hall mobility greater than 5500 cm2/V-s at room temperature can be obtained routinely (1,2).…”