Development of an assembly process and reliability investigations for flip-chip LEDs using the AuSn soldering

Elger, Gordon; Hütter, Matthias; Oppermann, Hermann; Aschenbrenner, R.; Reichl, H.; Jager, Edwin

doi:10.1007/s005420100103

Cited by 60 publications

(30 citation statements)

References 1 publication

(1 reference statement)

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“…We present initial results on large area flip-chip mounted HB-LEDs that employ electroplated Au/Sn/Au for the flip-chip assembly. This lead-free solder can be bonded without flux and has the potential of reliable operation [7,8]. In our approach more than 65% of the chip surface is in direct contact with the solder.…”

Section: Introductionmentioning

confidence: 99%

LED flip‐chip assembly with electroplated AuSn alloy

Maaskant¹,

Akhter²,

Cordero³

et al. 2005

phys. stat. sol. (c)

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PACS 78.66.Fd, 81.15.Pq, 85.30.De, 85.60.Jb InGaN based high brightness (HB)-LED chips have been fabricated and bonded to substrates that were coated with electroplated Au/Sn/Au solder. The assemblies yielded a forward voltage of 5.6 V and an optical output power of 42 mW when tested at 1,000 mA bias. The electroluminescence distribution was mapped with a CCD camera to determine the current spreading into the p-contact region. Computational fluid dynamics (CFD) was used to check the effect of non-uniform current spreading on the thermal resistance of the assemblies. We show that a good knowledge of the non-uniform heat generation is required to obtain accurate modelling results. The bond strength of the AuSn solder joints exceeded the norm, when shear tested according to MIL-STD-883E (method 2019.5).

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Section: Introductionmentioning

confidence: 99%

LED flip‐chip assembly with electroplated AuSn alloy

Maaskant¹,

Akhter²,

Cordero³

et al. 2005

phys. stat. sol. (c)

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“…In this phase diagram, there are many varieties of IMC phases [11,12]. However, of all these phases, AuSn, AuSn2, and AuSn4 are confirmed by previous studies [3,4,13]. These phases appear in the solder microstructure at the room temperature while Au-rich phase and Au5Sn, could not be completely distinguished as they could be at the resolution limit of conventional techniques [14].…”

Section: Introductionmentioning

confidence: 72%

Microstructural and Diffusion Analysis of Au-Sn Diffusion Couple Layer Undergoing Heat Treatment at Near Eutectic Temperatures

Darayen¹,

Athichalinthorn²,

Techapiesancharoenkij³

et al. 2017

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Abstract. Diffusion couples of pure gold and pure tin were created by mechanical cold rolling method. The couples were isothermally treated at temperatures slightly above and below the eutectic temperature near tin-rich region of the equilibrium phase diagram. Differences in the diffusion behaviors were observed as a function of treatment temperatures below (473 K) and above (498 K) the eutectic temperature. At the boundary, it was found that first solid state inter-diffusion was initiated which resulted in local compositional change and solid-state formation of intermetallic compounds (IMCs). As the composition shifts away towards mixing, the growth of the intermetallic phases was monitored as a function of temperature and time. At temperature above the eutectic, there may be a liquid fraction as the interface isothermally melted. The kinetic involves dissolution of Au atoms into localized tin-rich liquid. At below eutectic temperature, the formation and growth kinetic of phases follows a solid state diffusion mechanism. By investigation the exponent n values in the growth equation l=k(t/t0)n, the values were found to be in between 0.62 -0.77 which implies that the kinetics of IMC formations experiment are controlled by both diffusion and intermetallic reaction. The bonding time was found to be faster and more reliable at bonding temperature slightly above the eutectic.

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“…Flip chip technology offers a promising solution with excellent electrical and thermal performance (Elger et al 2002) owing to the advantages of high I/O counts, short interconnection length (Yoon et al 2007) and small interconnection resistance (Wolf et al 2006). During the flip chip packaging process, the mechanical vibration of packaging devices and the thermal expansion mismatch of materials may induce defects to solder bumps, such as missing solder bumps, voids, and cracks (Verma and Han 2004).…”

Section: Introductionmentioning

confidence: 99%

Flip chip solder bump inspection using vibration analysis

et al. 2012

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Flip chip technology is an attractive choice for high-density packaging and complex microsystem architectures. A critical element in the successful application of flip chip technology is the reliability of solder bumps. In this paper a nondestructive detection method is presented for the flip-chip solder bump inspection using ultrasonic excitation and vibration analysis. Simulations are implemented to explore the feasibility of this method, and experimental investigations are also performed, where the flip chips are excited by continuous ultrasonic waves and their vibration velocities are measured by a laser scanning vibrometer for further analysis. The results reveal that the defective chips can be distinguished from the good chips by the chip vibration velocities with the feature coefficient a, which proves the effectiveness of this method. Therefore, it may provide a new path for the improvement and innovation of flip chip on-line inspection systems.

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Development of an assembly process and reliability investigations for flip-chip LEDs using the AuSn soldering

Cited by 60 publications

References 1 publication

LED flip‐chip assembly with electroplated AuSn alloy

LED flip‐chip assembly with electroplated AuSn alloy

Microstructural and Diffusion Analysis of Au-Sn Diffusion Couple Layer Undergoing Heat Treatment at Near Eutectic Temperatures

Flip chip solder bump inspection using vibration analysis

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