Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model

Luo, Yong; Lubeck, O.; Wasserman, Harvey J.; Bassetti, Federico; Cameron, Kirk W.

doi:10.1145/287318.287351

Cited by 15 publications

(10 citation statements)

References 10 publications

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“…The input to our analytical model includes system parameters as well as per-thread parameters listed in Table I. Our model is based on the additive CPI model used in modeling cache performance of uniprocessor systems [22], [23], [24]. We extend the model to a CMP system in which Fraction of off-chip bandwidth assigned to thread i multiple threads run together and result in contention on offchip bandwidth.…”

Section: B Model Formulationmentioning

confidence: 99%

“…We model the off-chip bus as a queuing system [25], in which contention results in queuing delay for off-chip memory requests. 1) Extending Uniprocessor CPI Model to a CMP System: The CPI model [22], [23], [24] states the average cycle it takes to execute an instruction in a uniprocessor with two levels of caches can be expressed as addition of CPI assuming an infinite L2 cache and the extra CPI due to L2 cache misses:…”

Section: B Model Formulationmentioning

confidence: 99%

“…To arrive at the goal, we propose an analytical model that is simple yet powerful enough to model the impact of bandwidth partitioning on performance. Our analytical model is built on top of the additive Cycle Per Instruction (CPI) model [22], [23], [24] and queuing theory [25], taking various system parameters (CPU frequency, cache block size, and peak available bandwidth), as well as application cache behavior metrics (various CPIs, and miss frequency) as input. Studying the model, coupled with results from empirical evaluation, we arrive at several interesting findings, among them are:…”

Section: Introductionmentioning

confidence: 99%

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Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance

Liu

Jiang

Solihin

2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

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Chip Multi-Processor (CMP) architectures have recently become a mainstream computing platform. Recent CMPs allow cores to share expensive resources, such as the last level cache and off-chip pin bandwidth. To improve system performance and reduce the performance volatility of individual threads, last level cache and off-chip bandwidth partitioning schemes have been proposed. While how cache partitioning affects system performance is well understood, little is understood regarding how bandwidth partitioning affects system performance, and how bandwidth and cache partitioning interact with one another.In this paper, we propose a simple yet powerful analytical model that gives us an ability to answer several important questions: (1) How does off-chip bandwidth partitioning improve system performance? (2) In what situations the performance improvement is high or low, and what factors determine that? (3) In what way cache and bandwidth partitioning interact, and is the interaction negative or positive? (4) Can a theoretically optimum bandwidth partition be derived, and if so, what factors affect it? We believe understanding the answers to these questions is very valuable to CMP system designers in coming up with strategies to deal with the scarcity of off-chip bandwidth in future CMPs with many cores on a chip.Index Terms-Chip Multi-Processor; shared cache; off-chip memory bandwidth; cache partitioning; off-chip memory bandwidth partitioning; 987-1-4244-5659-8/09/$25.00 ©2009 IEEE

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Section: B Model Formulationmentioning

confidence: 99%

Section: B Model Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance

Liu

Jiang

Solihin

2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

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“…the overall CPI is the sum of CPI assuming an infinite cache and additional CPI when cache misses are considered [7,13]. Specifically, assuming a system with two levels of caches, we use Luo's model [13] that expresses CPI as:…”

Section: Criteria For Resource Stealingmentioning

confidence: 99%

A Framework for Providing Quality of Service in Chip Multi-Processors

Ottoni

August

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse in terms of performance, reliability, and availability requirements. It can be expected that more and more applications with diverse requirements will run on a CMP and share platform resources such as the lowest level cache and off-chip bandwidth. In this environment, it is desirable to have microarchitecture and software support that can provide a guarantee of a certain level of performance, which we refer to as performance Quality of Service.In this paper, we investigate a framework that would be needed for a CMP to fully provide QoS. We found that the ability of a CMP to partition platform resources alone is not sufficient for fully providing QoS. We also need an appropriate way to specify a QoS target, and an admission control policy that accepts jobs only when their QoS targets can be satisfied. We also found that providing strict QoS often leads to a significant reduction in throughput due to resource fragmentation. We propose novel throughput optimization techniques that include: (1) exploiting various QoS execution modes, and (2) a microarchitecture technique that steals excess resources from a job while still meeting its QoS target. We evaluated our QoS framework with a full system simulation of a 4-core CMP and a recent version of the Linux Operating System. We found that compared to an unoptimized scheme, the throughput can be improved by up to 47%, making the throughput significantly closer to a non-QoS CMP.

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“…Empirically, we could determine a more accurate value for the fraction of the memory penalty that is exposed to each application using an approach similar to the one presented in [38]. However, we presented this last step to validate the ideas that are at the base of our performance prediction method.…”

Section: Predictions For Mips R12000mentioning

confidence: 99%

Application Insight Through Performance Modeling

Marin

Mellor-Crummey

2007

2007 IEEE International Performance, Computing, and Communications Conference

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Tuning the performance of applications requires understanding the interactions between code and target architecture. Hardware counters, present in all modern processors, can identify possible causes of performance problems and can pinpoint sections of code that execute at a low fraction of machine peak performance. However, the information provided by hardware counters is often insufficient to understand the causes of poor performance or to realistically estimate the potential for performance improvement.This thesis presents techniques to measure and model application characteristics independent of the target architecture. Using information gathered from both static and dynamic analysis, this approach not only makes accurate predictions about the behavior of an application on a target architecture for different inputs, but also provides guidance for tuning by highlighting the factors that limit performance at different points in a program. We introduce several new performance analysis metrics that estimate the maximum gain expected from tuning different aspects of an application, or from using hardware accelerator coprocessors. Our approach models the most important factors affecting application performance and provides estimates of unfulfilled performance potential due to a mismatch between an application's characteristics and the resources present on the target architecture. We model an application's instruction execution cost and memory hierarchy utilization, and we identify performance problems arising from insufficient instruction-level parallelism or poor data locality.To demonstrate the utility of this approach, this thesis presents the results of analyzing and tuning two scientific applications. For Sweep3D, a three-dimensional Cartesian geometry neutron transport code benchmark from the DOEs Accelerated Strategic Computing Initiative, our analysis identified opportunities for improvement that shortened execution time by 66% on an Itanium2-based system. For the Gyrokinetic Toroidal Code (GTC) from Princeton Plasma Physics Laboratory, a particlein-cell code that simulates turbulent transport of particles and energy in burning plasma, our techniques identified opportunities for improvement that shortened execution time by 33% on the same Itanium2 system.

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Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model

Cited by 15 publications

References 10 publications

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance

A Framework for Providing Quality of Service in Chip Multi-Processors

Application Insight Through Performance Modeling

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