Designing VFs by applying genetic algorithms from nullator-based descriptions

Abstract

An automatic method is proposed to design CMOS compatible voltage followers (VFs) by applying genetic algorithms. It is described how an automatic system can deals with huge search spaces to design practical VFs by performing evolutionary operations from nullator-based descriptions. The proposed method consists of three main steps: generation of the small-signal circuitry, addition of biases, and sizing by using standard CMOS technology of 0.35µm. Furthermore, it is described how to synthesize VFs by codifying the three main steps into three kinds of genes, and how to select small-signal, biased, and sized topologies to generate potential solutions. Finally, several applications are discussed along with the evolution of VFs to design current conveyors.

A New Approach to Biasing Design of Analog Circuits

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Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

“…Note that eight distinct values for the fixators are provided (two zeros are not shown). For the norators, the first one is a CCCS and the next three are CCVS, all with gain of 10 9 . The result of the simulation is also given below.…”

Local biasing and the use of nullator-norator pairs in analog circuits designs

“…The use of nullor pair in analog designs has been very extensive [7][8][9]. Telelo-Cuautle also introduces biasing techniques for amplifiers at nullor levels [10,11].…”