Designing pipelined systems with a clock period approaching pipeline register delay

Tatapudi, S.B.; Delgado-Frias, J.G.

doi:10.1109/mwscas.2005.1594240

Cited by 6 publications

(6 citation statements)

References 7 publications

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“…The minimum clock period of 2.689ns is produced and the clock frequency is 371.8MHz. The pipelined organization requires sophisticated complication techniques for modem processors [16]. The given MBM is able to test the pipelining approach in order to reduce the critical path.…”

Section: Implementation Resultsmentioning

confidence: 99%

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

Kaur¹,

Patial²

2013

IJCA

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This paper presents 16×16 bit Radix-4 Modified Booth's Multiplier (MBM) optimized for high speed multiplication by using pipeline Technique. This paper aims at reduction of hardware utilization. This is accomplished by the use of 3:2 compressor adders. An efficient VHDL code has been written, successfully simulated on Modelsim 10.2 simulator and Xilinx 12.4 navigator is used for synthesizing the code. Simulation result shows the clock period of 2.689ns. The selected device to synthesize the code is xc3s500e-4pq208 of Sartan-3E family. The area utilization is shown as 222 numbers of slices and 383 numbers of LUTs. General Terms: Multiplier, Pipelining Technique

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Section: Implementation Resultsmentioning

confidence: 99%

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

Kaur¹,

Patial²

2013

IJCA

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“…The mesochronous pipeline scheme (MPP) [10], [11], [12] modifies CPP scheme to gain higher performance, simplify the clock distribution and reduce power consumption. In the MPP scheme, like in the CPP scheme, a digital system is partitioned into pipeline stages.…”

Section: Mesochronous Pipeline Architecturementioning

confidence: 99%

“…The clock period of the MPP scheme is defined by (2). A complete derivation of (2) is presented in [11], [12].…”

Section: Mesochronous Pipeline Architecturementioning

confidence: 99%

“…A number of simulations have been performed on the full adder to precisely characterize performance of this cell. The propagation delay for the full adder varied from 210ps (d min ) to 280ps (d max ), resulting in a maximum delay variation of 70ps [10], [11]. From simulations of the D flip-flop, the clock-to-output delay is approximately 130ps, set-up time is 65ps, and hold time is 5ps.…”

Section: Performancementioning

confidence: 99%

“…While asynchronous pipelining may be appealing since it completely eliminates the need to distribute clock, it is complex compared to synchronous schemes [8], [9]. Our Mesochronous pipeline (MPP) scheme [10], [11], [12] modifies the pipeline architecture to address the power issues and also achieve higher performance.…”

Section: Introductionmentioning

confidence: 99%

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A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

Tatapudi

Delgado-Frias

2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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Abstract-A mesochronous pipeline scheme is described in this paper. In a conventional pipeline scheme each pipeline stage operates on only one data set at a time. In the mesochronous scheme, pipeline stages operate on multiple data sets simultaneously. The clock period in conventional pipeline scheme is proportional to the maximum pipeline stage delay while in mesochronous pipelining, it is proportional to the maximum pipeline stage delay difference, which means higher clock speeds are possible and number of pipeline stages is significantly less. In mesochronous approach the clock distribution network is simple and load on it is less resulting in significant power savings. Also, the variations in supply current drawn by clock network is significantly less in mesochronous scheme, thus power supply noise (IR drop and Ldi/dt noise) is less. An 8×8-bit multiplier using carry-save adder technique has been implemented in conventional and mesochronous pipeline approach using TSMC 180nm (drawn length 200nm). The over all power dissipation in mesochronous approach is less than 50% of the power dissipation in conventional approach. In conventional approach, the power dissipation in clock network and pipeline registers is close to 80% of total power dissipation, while in mesochronous approach logic dissipates more power.Index Terms-pipelined systems, high performance, mesochronous pipelining, multipliers, low power.

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A mesochronous pipeline scheme for high performance low power digital systems

Delgado-Frias

2006 IEEE International Symposium on Circuits and Systems

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Designing pipelined systems with a clock period approaching pipeline register delay

Cited by 6 publications

References 7 publications

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

A mesochronous pipeline scheme for high performance low power digital systems

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