2009 International Semiconductor Device Research Symposium 2009
DOI: 10.1109/isdrs.2009.5378256
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Designing bulk-driven MOSFETs in scaled technologies

Abstract: With the advent of system-on-a-chip integration, analog components are being forced to co-exist with their digital counterparts in scaled processes where the supply voltage, V DD , is expected to fall to 0.7 V by 2012 [1]. As a result of this integration, traditional analog topologies suffer from voltage headroom constraints since the threshold voltage, V T , can no longer scale proportionately with V DD due to sub-threshold leakage constraints. In 1996, Blalock described how the bulk terminal of a MOSFET coul… Show more

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“…4 nm; the channel length, L = 400 nm and y epi = 5 nm) [23]. Note that normalization set g mb and g m equal to 1 at t ox = 1.4 nm.…”
Section: Simulation Setupmentioning
confidence: 99%
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“…4 nm; the channel length, L = 400 nm and y epi = 5 nm) [23]. Note that normalization set g mb and g m equal to 1 at t ox = 1.4 nm.…”
Section: Simulation Setupmentioning
confidence: 99%
“…The dependence of g mb and g m on t ox is depicted in figure 2 excluding the influence of polysilicon gate depletion [23].…”
Section: Impact Of T Ox Scalingmentioning
confidence: 99%
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