Design space exploration for multicore architectures

Monchiero, Matteo; Canal, Ramón; González, Antonio

doi:10.1145/1183401.1183428

Cited by 71 publications

(39 citation statements)

References 23 publications

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“…As expected, some differences were obtained mainly due to the different architecture organization modeled in both simulators as well as the different instruction set architectures. Moreover, the overall distribution of the power consumption among the main hardware structures presented in a tiled chip multiprocessor agree with the results reported by different researchers [17,19,25].…”

Section: Validation Of the Power Model Of Sim-powercmpsupporting

confidence: 89%

“…As expected, it can be observed that most of the power is dissipated in the processor cores of the CMP. In particular, the ALU reveals as one of the most consuming structures of the CMP, as reported in [17]. Regarding the caches (private L1 caches and the shared multibanked L2 cache), we can see that their fraction of the total power is quite significant.…”

Section: Experimental Frameworkmentioning

confidence: 69%

“…In [6], Chen et al present SimWattch, a full system energy simulator based on Simics (a system level simulation tool) and Wattch. In [17], a characterization for multicore architectures is presented using a modified version of SESC simulator [18] that uses Wattch power models.…”

Section: Related Workmentioning

confidence: 99%

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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

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Section: Validation Of the Power Model Of Sim-powercmpsupporting

confidence: 89%

Section: Experimental Frameworkmentioning

confidence: 69%

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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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“…Functional units can also be resized to accommodate a lower power density [23], but with a reduction of the clock frequency and negative impact on processor performance. Floorplan can also be conveniently designed to accommodate thermal hot-spots as done in [19].…”

Section: A Design-time Thermal Optimizationmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-Multi-core architectures are a promising paradigm to exploit the huge integration density reached by highperformance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM techniques.

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“…Efforts in high-k materials have reduced the gate-oxide leakage; nevertheless lower voltages increase dramatically subthreshold leakage. Both academic and industrial studies show that a large part of the power consumption of a state-of-the-art processor is due to the static component [1]- [3]. According to the ITRS [4], efficiently managing low-leakage devices and operation modes is a key challenge for next generation systems.…”

Section: Introductionmentioning

confidence: 99%

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Monchiero

Canal

González

2009

2009 International Conference on Parallel Processing

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Abstract-This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches.Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar.

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Design space exploration for multicore architectures

Cited by 71 publications

References 23 publications

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Thermal/performance trade-off in network-on-chip architectures

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

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