Design Optimization of AlInAs–GaInAs HEMTs for High-Frequency Applications

Abstract

By using a Monte Carlo simulator, the static and dynamic characteristics of 50-nm-gate AlInAs-GaInAs-doped high-electron mobility transistors (HEMTs) are investigated. The Monte Carlo model includes some important effects that are indispensable when trying to reproduce the real behavior of the devices, such as degeneracy, presence of surface charges, T-shape of the gate, presence of dielectrics, and contact resistances. Among the large quantity of design parameters that enter the fabrication of the devices, we have studied the influence on their performance of two important factors: the doping level of the-doped layer, and the width of the devices. We have confirmed that the value of the-doping must be increased to avoid the reduction of the drain current due to the depletion of the channel by the surface potential. However, a higher-doping has the drawback that the frequency performance of the HEMTs is deteriorated, and its value must be carefully chosen depending on the system requirements in terms of delivered power and frequency of operation. The reduction of the device width has been also checked to improve the cutoff frequencies of the HEMTs, with a lower limit imposed by the degradation provoked by the offset extrinsic capacitances.

Monte Carlo study of the noise performance of isolated-gate InAs HEMTs

“…MC results for SSEC parameters have been extracted from the Y-parameters calculated by Fourier analysis of the transistor current response to voltage steps applied at the gate and drain contacts [9]. In order to compare the intrinsic experimental equivalent circuit parameters with the simulated ones, three geometric capacitances, extr gs C , extr gd C , and extr ds C (intrinsic from the point of view of measurements but extrinsic from the point of view of simulations), have been included [5,8].…”

“…In our simulation model the gate leakage current, I G , has not been considered. A gate-drain resistance and a gate-source resistance, r gd and r gs , in parallel with C gd and C gd , respectively, have been included in the SSEC in order to consider the existence of a non-zero gate current [8,9]. We have adopted values for r gd and r gs of 12 KW and 14.6 KW, respectively, in good agreement with the values of gate resistance that can be estimated from the measurements of I G vs. V GS .…”

“…5. When the frequency increases, the SSEC is not valid anymore and neither the values of the extrinsic elements; therefore, the value of f T is calculated by extrapolating the low frequency dependence of |H fe | 2 [9].…”

Monte Carlo modelling of noise in advanced III–V HEMTs

“…In this work we will review the noise modelling of InGaAs and InAs HEMTs performed with a 2D ensemble MC simulator, the validity of which has been checked by means of the comparison with experimental results of static characteristics, small signal behavior and noise performance of fabricated HEMTs [13,19]. Using this MC simulator as analyzing tool, we can optimize the values of some key technological parameters, thus providing some useful design rules for the fabrication of HEMTs aiming to high-frequency and/or lownoise applications [20,21].…”

Monte Carlo analysis of memory effects in nano‐scale rectifying diodes

“…Details can be found in [4][5][6]. The simulation is carried out only in the InGaAs channel layer which contains the 2DEG.…”