Design Optimization of AlInAs–GaInAs HEMTs for Low-Noise Applications

Monte Carlo study of the noise performance of isolated-gate InAs HEMTs

“…Due to the important uncertainty in the calculation of the gate current noise, the MC values for R and C are not very precise. Overall, the values of P, R and C in the HEMT under study are similar to those obtained in InGaAs HEMTs [10], with an improvement mainly in R, which under low noise conditions (low current level, around 10 mA/mm) is as low as about 0.14 for a 225 nm gate length device. This is due to the almost perfect confinement of electrons in the channel, avoiding the real space transfer and decreasing the gate current noise.…”

“…Due to the reduced value of the gate current noise, excellent values of F min 0.3 dB@10 GHz and 2.0 dB@94 GHz have been found, even if the cutoff frequency of the transistor is not especially high (as expected for a 225 nm gate length). In fact, these values are better than those found in InGaAs HEMTs with a much shorter gate length of 50 nm (with similar values of associated gain at 10 GHz, about 15 dB, and noise resistance, less than 20 ) even if the cutoff frequencies of the InAs HEMT are about the half [10]. The only problem is that this lower cutoff frequency degrades the associated gain at high frequency, only about 2 dB@94 GHz, lower than that obtained in 50 nm gate InGaAs HEMTs (about 6 dB).…”

Monte Carlo analysis of the dynamic behavior of III–V MOSFETs for low-noise RF applications

“…the optimum matching conditions of noise are thus very difficult to achieve. This value is significantly reduced in COMB-MOS: 55 Ω at 20 GHz, which is comparable to that reported in a HEMT structure [42]. is dramatically less in Si BULK-MOS: NFmin is significantly higher (2 dB) and the bandwidth of transducer power gain is strongly reduced in this matching conditions, Ga is only 4 dB at 20 GHz for ID = 110 µA/µm.…”

“…It should be mentioned that these poor performance for Si-device are achieved at low VDS and could be improved at nominal power supply of 1.2 V but at the cost of a strong increase of the power consumption. All these noise performances are reported in Table 2 together with results from experiments [45] and from other numerical investigations on several FET architectures: HEMT [42] [38] , LAC (Laterally Asymmetric Channel) [44] and FDSOI (Fully depleted SOI) [46]. Gm/ Gd…”

Numerical modeling of TeraHertz electronic devices

“…[38]. Figure 4(a) shows the gate current noise spectra for several values of the drain-to-source voltage and V GS = 0.05 V obtained with MC simulations of similar HEMTs (those studied in [41]). There are two maxima on each spectrum: the low frequency (LF) one around 2 THz and the high frequency (HF) one at 5 THz.…”