Design of SOI FinFET on 32nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Cho, Seongjae; Lee, Jung Hoon; O’uchi, S.; Endo, Kazuhiko; Masahara, Meishoku; Park, Byung Gook

doi:10.1016/j.sse.2010.05.013

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…23 GIDL occurs due to the high reverse bias between the silicon body and the drain junction (a PN-junction) near the gate edge at a nearzero or a negative gate bias. 24 GIDL usually increases as the gate length (L g ) decreases due to the floating body effect and is usually pronounced in short-channel devices. In this paper, we pick the GIDL slope to quantify this effect; the larger this slope the lesser GIDL effect the device has.…”

Section: Gidlmentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Gidlmentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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show abstract

“…It can trace the point where the curvature most rapidly changes. At this point, drastic enhancement in GIDL begins to occur [31]. In a physical sense, this is more reliable than the conventional method [29].…”

Section: Design Of Low Standby Power (Lstp) Soi Finfetmentioning

confidence: 89%

“…However, in simulation works, GIDL can be quantitatively evaluated by switching on and off the set of GIDL-related models. In a previous research, only BTBT model was switched but it is more realistic to deal with all the related models simultaneously [29][30][31]. In Fig.…”

Section: Design Of Low Standby Power (Lstp) Soi Finfetmentioning

confidence: 99%

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

Cho¹,

O’uchi²,

Endo³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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“…Generally, the GIDL is reduced by optimizing the overlap=underlap of the doped region with the gate electrode. 30) The dependence of the GIDL on T fin and the extension-I=I species is a specific phenomenon in FinFETs. In the case of state-of-the-art FinFETs with a physical L g of 20 nm or less, T fin is set smaller than 20 nm to suppress the short-channel effect.…”

Section: Gidl Analysismentioning

confidence: 99%

Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage

Matsukawa

Liu

Mori

et al. 2016

Jpn. J. Appl. Phys.

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The influence of the extension doping conditions on gate-induced drain leakage (GIDL) has been investigated to optimize fin field-effect transistors (FinFETs) for ultralow-power (ULP) applications. An increased GIDL for a smaller fin thickness and a dependence on the implanted ion species, i.e., a larger GIDL for As than for P, are recognized. These results suggest that the residual defects due to extension doping increase the GIDL, and the suppression of the defects by the optimization of the doping process is the key to the optimization of FinFETs for ULP applications.

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Design of SOI FinFET on 32nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Cited by 7 publications

References 5 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage

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