Design of 32-bits RISC processor for hardware efficient QR decomposition

Omran, Safaa S.; Abdul-abbas, Ahmed K.

doi:10.1109/icasea.2018.8370958

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…Commonly, the Gram Schmidt process, Householder Transformation and Givens Rotations are known as the most widely used algorithms for QR decomposition. The Householder Transformation and givens rotations illustrate the feature of numerical stability while the Gram-Schmidt process provides an occasion to perform successive orthogonalization [9]. In this paper the Gram-Schmidt orthonormalization algorithm and Givens Rotation algorithm together are used for the decomposition of matrix (A).…”

Section: Qr Decompositionmentioning

confidence: 99%

Multi core processor for QR decomposition based on FPGA

Omran

Abdul-abbas

2018

IJET

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Hardware design of multicore 32-bits processor is implemented to achieve low latency and high throughput QR decomposition (QRD) based on two algorithms which they are Gram Schmidt (GS) and Givens Rotation (GR). The orthogonal matrices are computed using the first core processor by Gram Schmidt algorithm, and the upper triangular matrices are computed using the second core processor by Givens Rotation algorithm. This design of multicore processor can achieve 50M QRD/s throughput for (4 × 4) matrices at running frequency 200 MHz.

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Section: Qr Decompositionmentioning

confidence: 99%

Multi core processor for QR decomposition based on FPGA

Omran

Abdul-abbas

2018

IJET

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“…2, July 2023: 165-173 166 can be lowered in pipelining forwarding and stalling techniques and Tomasulo algorithms [1], [2]. The pipelining without interlocked stages is implemented in Harvard-type architecture to ensure no deadlocks occur between the stages of the pipelining and area, power, and delay are reduced [3], [4]. The QR decomposition core for the FPGA processor is developed for the 32-bit RISC processor.…”

Section: Introductionmentioning

confidence: 99%

A novel reduced instruction set computer-communication processor design using field programmable gate array

Prathap¹,

Ramesh

2023

IJRES

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In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.

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Industry 4.0 CAMI: An Elastic Cloud Zynq UltraScale FPGA Metering Architecture

Okafor

Obayi

2020

Computational Science and Its Applications – ICCSA 2020

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In the era of Industry 4.0, commoditized services (such as electricity, healthcare, etc.), require accuracy, availability, security and Quality of service (QoS) in the Cloud space. This paper presents cloud advanced metering infrastructure (CAMI) using Zynq UltraScale+ device field programmable gate array (FPGA). The architectural layout for energy tracking and profile measurement is discussed. Unlike existing systems with digital signal processors, it uses precision-based meter reading with encryption driven demand side management (DSM) to protect end-users. An energy service application with supporting hardware prototype is designed. Cryptographic algorithms, dynamic auto-scaling and predictive QoS provisioning are introduced as features of its backend cloud virtualization Infrastructure controller (CVIC). Process integration is achieved with CVIC synthesis for energy analytics and DSM. For the use case scenario, the CAMI prototype runs on Zynq UltraScale+ device with support for end-to-end dataset captures. The system provides on-demand visualization of energy consumption patterns for the end-users. In the experimental setup, two case scenarios demonstrate how the metering system executes fast edge computing profiling. Optimal performance is achieved for latency, utilization, and throughput under CVIC overhead constraint. It was observed that resource utilization responses for heterogeneous and non heterogeneous CVIC are 71.43% and 28.57% respectively. Latency profiles gave 71.43% and 28.57% respectively. With the VM controller, FPGA CAMI offered 47.36% while without VM controller, 52.63% throughput is observed. Consequently, the results highlights how FPGA hardware acceleration can significantly improve request distribution as well as workload processing for cloud based metering systems.

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Design of 32-bits RISC processor for hardware efficient QR decomposition

Cited by 5 publications

References 5 publications

Multi core processor for QR decomposition based on FPGA

Multi core processor for QR decomposition based on FPGA

A novel reduced instruction set computer-communication processor design using field programmable gate array

Industry 4.0 CAMI: An Elastic Cloud Zynq UltraScale FPGA Metering Architecture

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