Design methodology of high performance on-chip global interconnect using terminated transmission-line

Zhang, Yulei; Zhang, Ling; Deutsch, A.; Katopis, G.A.; Dreps, Daniel; Buckwalter, James F.; Kuh, E.S.; Cheng, Chung‐Kuan

doi:10.1109/isqed.2009.4810337

Cited by 12 publications

(2 citation statements)

References 15 publications

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“…still do not appear as significantly. Recently, a design methodology for implementation of singleended on-die transmission lines for a 45 nm technology node was developed, and simulations were carried out using 2D EM field solver [3]. The analyzed 5 mm long transmission line models were not implemented by standard metal layers for the technology node, but specially designed and widened.…”

Section: On-die Transmission Linesmentioning

confidence: 99%

Inter-symbol interference (ISI) in on-die transmission lines

Rysin

Livshits

Sofer³

et al. 2009

2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems

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The waveforms of a signal transmitted through single-ended on-die transmission lines, implemented by standard metal layers of a CMOS 45 nm technology node, have been experimentally studied. The influence of the active loss level of the lines, as well as of the impedance mismatch between the transmission line and its driver upon the signal distortion, and particularly upon the inter-symbol interference, is discussed.Index Terms -VLSI, on-chip interconnections, inter-symbol interference, global wiring, on-chip transmission line, transmission line.

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Section: On-die Transmission Linesmentioning

confidence: 99%

Inter-symbol interference (ISI) in on-die transmission lines

Rysin

Livshits

Sofer³

et al. 2009

2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems

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“…At the same time, skin effect and dielectric losses lead to attenuation of the Highfrequency harmonic components (Arabi et al, 1991;Svensson and Dermer, 2001). As a result, the signals will be distorted, which is often regarded as a signal integrity problem (Zhang et al, 2009;Johnson and Graham, 2003). However, the influences of signal distortions on interconnect reliability are seldom discussed.…”

Section: Introductionmentioning

confidence: 99%

Impact of Skin Effect, Resistive and Dielectric Losses on Current Estimation and Reliability of ULSI Interconnects

Yao¹,

Zhang²,

Zhao³

2013

RJASET

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In this study, a series connection system of interconnects and gates is studied. In the system, we focus on skin effect, resistive and dielectric losses in previous level interconnects and the impact of their variations on the fast current estimation and the lifetime calculation of the post level interconnects. The changes in cross-section dimensions of interconnects are used to represent their differences in resistances, dielectric losses and skin effect in actual circuits or to represent the process of Electro Migration (EM). Through the analysis of the voltage transfer function of interconnects, the different roles of skin effect, resistive and dielectric losses in signal attenuation for interconnects of various cross-sections are pointed out. The study shows that the input voltage waveforms of the post level interconnects will change if the cross-section sizes of the previous level interconnects vary. By means of showing the changing tendencies of current and lifetime estimation results affected by the cross-section dimensions of the previous interconnects, we indicate that the fast current and reliability estimation results will not be accurate enough if these effects are not included.

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Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Jangam

Pal

Bajwa

et al. 2017

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

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Abstract-In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm 2 ) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and low cross-talk (<-15 dB). With fine interconnect pitches (<10 μm), our scheme can achieve >5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.

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Design methodology of high performance on-chip global interconnect using terminated transmission-line

Cited by 12 publications

References 15 publications

Inter-symbol interference (ISI) in on-die transmission lines

Inter-symbol interference (ISI) in on-die transmission lines

Impact of Skin Effect, Resistive and Dielectric Losses on Current Estimation and Reliability of ULSI Interconnects

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

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