“…The Spartan 3 FPGA architecture includes also 16 embedded [18x18] hardware multipliers, 18Kb internal bloc RAM memories and enhanced configurable Input/Output blocs (IOBs). The architecture of each control algorithm is designed according to an efficient design methodology [16], [17], that offers considerable design advantages such as reusability, reduction of the development time and optimization of the consumed resources… Basing on this methodology, each control algorithm is partitioned into elementary modules, which are easier to develop and, which make sense from a functional point of view. Fig.7 presents the general structure [18], [19].…”