Design and validation of execution schemes for dynamically reconfigurable architectures

Oppold, T.; Eisenhardt, Sven

doi:10.1109/fpt.2006.270346

Cited by 4 publications

(4 citation statements)

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“…Since the interconnect resources can be reused in different contexts, similar penalties resulting from poor routability can be expected for the different architectures customized for one application. The implications of excessive register requirements are discussed in [10]. The last column in the table compares this IP-core to a customized statically reconfigurable architecture that uses the same II but does not reuse the FUs.…”

Section: Evaluation Of Areamentioning

confidence: 99%

“…On the other hand, using the stable tool chain of commercial architectures enables the evaluation of complex applications more efficiently. Since NEC's DRP (Dynamically Reconfigurable Processor) architecture [9] is very similar to the CRC model with respect to run-time reconfiguration [10], we can use the silicon-proven DRP and its associated tools [13] to get additional evaluation data.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Area and Performance by Processor-Like Reconfiguration

Oppold

Eisenhardt

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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It is well known that the area efficiency of a digital circuit can be improved by reconfiguration due to the reuse of resources. In this paper, we show that this benefit can be achieved for a wide range of applications if the reconfiguration can take place within each clock cycle, and we quantify the benefit by area estimations from a synthesizable architecture model. Although reconfiguration typically involves a decrease of performance, we show how performance can actually be increased by redirecting communication through the time domain. This increase is quantified by estimations from a silicon-proven commercial architecture and its associated compiler.

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Section: Evaluation Of Areamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of Area and Performance by Processor-Like Reconfiguration

Oppold

Eisenhardt

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…The CRC model can be configured with a variety of parameters in order to create different architecture instances. More details on the CRC model can be found in [4].…”

Section: Architecture Designmentioning

confidence: 99%

“…Details on this example and results of mapping it for different DIRs onto instances of the CRC model are presented in [4]. To demonstrate the benefits of processor-like reconfiguration, it is assumed in the following that the input values xr, xg, and xb are provided by the surrounding environment in 3 different clock cycles of a continuous stream and that the clock speed is 200 MHz.…”

Section: Besides Identifying Beneficial Compilation Techniques and Armentioning

confidence: 99%