2017 Iranian Conference on Electrical Engineering (ICEE) 2017
DOI: 10.1109/iraniancee.2017.7985431
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Design and simulation of a 3rd-order Discrete-Time Time-Interleaved delta-sigma modulator with shared integrators between two paths

Abstract: obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/o… Show more

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