2006
DOI: 10.1145/1150019.1136497
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Abstract: Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the current trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. Th… Show more

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Cited by 275 publications
(151 citation statements)
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“…Low-latency fat RC-based wires have been employed to speed up coherence signals in a CMP environment [10] and L1 cache access in a clustered architecture [2]. A recent paper by Li et al [23] proposes the implementation of a NUCA cache in three dimensions. A three-dimensional grid topology is employed and given the low latency for inter-die communication, a dynamic time division multiplexing bus is employed for signal broadcast across dies.…”
Section: Related Workmentioning
confidence: 99%
“…Low-latency fat RC-based wires have been employed to speed up coherence signals in a CMP environment [10] and L1 cache access in a clustered architecture [2]. A recent paper by Li et al [23] proposes the implementation of a NUCA cache in three dimensions. A three-dimensional grid topology is employed and given the low latency for inter-die communication, a dynamic time division multiplexing bus is employed for signal broadcast across dies.…”
Section: Related Workmentioning
confidence: 99%
“…Inter-die communication happens on interdie (or die-to-die) vias that are simply an extension of the vias used to access each die's metal stack. A collection of these inter-die vias is referred to as an "inter-die via pillar" [16]. Thus, a register value in the lower die can now be driven vertically on an inter-die via pillar to a metal layer on the die above and then routed horizontally to the unit on the upper die that needs the value.…”
Section: Proposed 3d Implementationmentioning
confidence: 99%
“…The simple extension of traditional NoC fabrics to the third dimension adding routers at each layer (Symmetric NoC), does not pay in performance due to the different delay between fast vertical TSV and the horizontal interconnects. A first proposal has been done by Li et al [8], with a network architecture embedded into the L2 cache memory. The use of Time-Division Multiple Access (dTDMA) buses as Communication Pillars between the wafers is proposed in order to have single-hop communication amongst the layers.…”
Section: Introductionmentioning
confidence: 99%