Design and development of a high-density, high-speed 10 kV SiC MOSFET module

Abstract

. The donation of substrates from DOWA, and financial support from the Engineering and Physical Sciences Research Council (EPSRC), RollsRoyce, and the CPES High Density Integration Consortium are greatly appreciated. Keywords«Silicon Carbide (SiC)», «Packaging», «High power density systems», «High voltage power converters», «MOSFET». AbstractHigh-density packaging of fast-switching power semiconductors typically requires low parasitic inductance, high heat extraction, and high thermo-mechanical reliability. High-density packaging of high-voltage power semiconductors, such as 10 kV SiC MOSFETs, also requires low electric field concentration in order to prevent premature dielectric breakdown. Consequently, in addition to the usual electromagnetic, thermal, and mechanical analyses, the electric fields must also be evaluated. This is the first detailed report on the optimization of a high-voltage SiC MOSFET power module.

Evaluation of the Imax-fsw-dv/dt Trade-off of High Voltage SiC MOSFETs Based on an Analytical Switching Loss Model

“…Finally, Fig. 5c compares the boundary current I ZVS in (20) with the I ZVS in [18], where the I ZVS is re-derived in (23) based on the MOSFET and the Schottky diode pair instead of the half-bridge topology in [18]. Although I ZVS is derived based on different assumptions and procedures from those in section 2, it matches well with the I ZVS , indicating that both assumptions and derivations in section 2 are reasonable.…”

“…. Since the design parameters of HV SiC MOSFETs are also missing in the literature, 4 groups of geometry parameters are assumed based on Cree's 2 nd generation SiC MOSFET [31] (w half-cell = 4.55 µm, d epi = 10 µm, N epi = 10 16 cm -3 ), including w half-cell = 5 µm, d epi = 14 µm, N epi = 10 16 cm -3 (1), w half-cell = 6 µm, d epi = 35 µm, N epi = 4 • 10 15 cm -3 (2), w half-cell = 6.55 µm, C oss +C D (pF) R th,jc (K/W) P D (W) 15 ˜10 1800.68 [5]* 2.00 * 4458 * 17.9 * 99 [10] 0.4375 [8] 160 10 ˜20 800.30 [5]* 2.58 [6] 4561 [7] 14.78 [7] 190 [7] 0.35 [22,23] 200 6.5 ˜30 338.13 [4] ˜45 87.15 [2]* 5.15 * 4700 [2] 10.58 [2] 298 [2,25] 0.296 [21] 236.5 1.2 ˜100 45.5 [26] 21.7 [26] 2788 [26] 16.14 [26] 463 [26,27] 0.27 [28] 259…”

“…In order to take full advantage of SiC MOSFETs' characteristics, low thermal resistance and high temperature withstanding power modules has been designed [21]. As a result, the junction-to-case thermal resistances R th,jc are adopted from [8] and [21] - [23] to describe the thermal limit accurately, while the missing R th,jc is interpolated, as illustrated in Fig. 3e.…”