Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay

Jayshree,; Seetharaman, G.

doi:10.1109/ahs.2018.8541441

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…2(b). This Schmitt trigger switches to an input signal faster than the CMOS buffer repeater presented in [13]. The Schmitt trigger is designed with NMOS and PMOS transistors, and PMOS width kept thrice of that of NMOS.…”

Section: Optimization With Schmitt Trigger As the Repeater And Taperingmentioning

confidence: 99%

Comparative Study of Hybrid Optimizations Technique for On-Chip Interconnect in Multimedia SoCs

Jayshree

Seetharaman

Pati

2021

Advances in Parallel Computing

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This paper presents the design and analysis of on-chip interconnect architectures for real time Multimedia Systems-on-Chip (MSoC) targeting Internet of Things (IoT) applications. The interconnect architecture provides high flexibility in connection for hardware implementation of reconfigurable neural network. Due to technology’s miniaturization in ultra-deep submicron technology, the on-chip interconnect performance and power consumption become a bottle-neck. In this paper, the hybrid optimization technique is proposed to address these challenges using schmitt trigger as a repeater and tapering. Here, the proposed optimization technique is incorporated with a dedicated point to point based interconnection (PTP-BI) configuration. A comparative study with others without optimization technique (Model–I) shows the effectiveness of the proposed optimization technique (Model–II). The technology node scaling impacts are also analyzed for both techniques. Finally, the percentage reduction of latency and power consumption are evaluated in two different cases to observe the impacts of varying the interconnect length.

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Section: Optimization With Schmitt Trigger As the Repeater And Taperingmentioning

confidence: 99%