Design and Analysis of Improved Phase-Transition FinFET Utilizing Negative Capacitance

Yadav, Sameer; Upadhyay, Pranshoo; Awadhiya, Bhaskar; Kondekar, P. N.

doi:10.1109/ted.2020.3043222

Cited by 18 publications

(6 citation statements)

References 25 publications

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“…The α, β, Ec, and Pr of PZT film are -6×10 10 cm/F, 5×10 18 cm 5 /(FC 2 ), 73 µC/cm 2, and 3 MV/cm, respectively. The α, β, Ec, and Pr of BTFM-CTO film is -5×10 9 cm/F, 2×10 17 cm 5 /(FC 2 ), 96 µC/cm 2 and 0.341 MV/cm, respectively. In our simulation, Cfe is not a fixed value, and it is calculated by solving self-consistently the Landau-Khalatnikov equation, which guarantees the accuracy of the simulation results.…”

Section: Theory and Model Of Nc-finfetmentioning

confidence: 95%

Critical parameters of gate control in NC-FinFET on GaAs

Jia

Zhang

et al. 2022

J Comput Electron

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： Gate control ability is expected to keep constant, guaranteeing accurate MOSFET adjustment of drive strength by changing its size. In NCFET, the non-uniform distribution of ferroelectric polarization and capacitance match are sensitive to the size and tend to enhance the fluctuation of gate control. In the current work, a detailed simulation was made on NC-FinFET to clarify the effect of structural factors on its gate control. These factors include the Fin structure (length, width, and height), the doping concentration in the GaAs channel, and ferroelectric film thickness. Simulation results indicate that the SS of NC-FinFET with BTFM-CTO film is more insensitive to the variation of structural factors than that with HfO2 or PZT film. Thus, the fluctuation of gate control can be significantly weakened with a suitable set of structure factors and ferroelectric parameters. The current work generates new insights into the fluctuation of gate control with varying structure factors and adjustment of NC-FinFET drive strength, which are essential for NC-FinFET to applicate in an analog circuit.

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Section: Theory and Model Of Nc-finfetmentioning

confidence: 95%

Critical parameters of gate control in NC-FinFET on GaAs

Jia

Zhang

et al. 2022

J Comput Electron

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“…A recent study has demonstrated the suitability of PTMs in the development of low-power dynamic circuits [5]. Moreover, it has been revealed that combining PTM with the negative capacitance effect improves the sub-threshold slope further and holds great promise for applications in digital devices and memories [6,7].…”

Section: Introductionmentioning

confidence: 99%

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Sorot,

Goel,

Rewari

2024

Phys. Scr.

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This research paper introduces a novel design for a Hybrid-CMOS Inverter using Vanadium Dioxide (VO2), a Phase Transition Material. The proposed Inverter exhibits a remarkably steep transition for falling logic at the output (1-0). By leveraging the Insulating to Metallic Current Density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS Inverter, the designed Inverter demonstrates several advantages. It achieves higher values of lower Noise Margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for the design of Inverters at lower Drain voltages, especially in devices operating at lower technology nodes. Furthermore, the Hybrid-CMOS Inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower Noise Margin and reduced values of leakage current.

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“…Fin field effect transistor (FinFET)-based complimentry metal oxide semiconductor (CMOS) logic devices are attaining popularity due to their high performance, low power, improved gate electrostatic, superior scalability, and low subthreshold slope (SS) when compared to the conventional FETs [1][2][3][4]. FinFETs fabricated on silicon-on-insulator (SOI) substrates * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Jaisawal

Rathore

Kondekar

et al. 2022

Semicond. Sci. Technol.

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One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/RF and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated TCAD models, to mitigate the leakage current, we analyzed the following approach to get HVT: 1) increasing channel doping (Nch′); 2) making drain-side underlap (Ldsu); 3) increasing gate length (Lg′). Two flavors of FinFETs viz Bulk and SOI (silicon-on-insulator) are suitably compared over their baseline counterpart, i.e., without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of Bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

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Design and Analysis of Improved Phase-Transition FinFET Utilizing Negative Capacitance

Cited by 18 publications

References 25 publications

Critical parameters of gate control in NC-FinFET on GaAs

Critical parameters of gate control in NC-FinFET on GaAs

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

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