1983
DOI: 10.1109/isscc.1983.1156557
View full text
|
|
Share

Abstract: A GaAs MSI 32b adder implemented in buffered FET logic (BFL) gates' that has been designed t o demonstrate the feasibility of the depletion-type GaAs ICs for LSI complexity will be reported.From the standpoint of high speed, simplified fabrication processing and a reasonable noise margin, a BFL gate constructed with depletion-type FETs is advantageous over the alternative logic gates in implementing GaAs LSI. However, the large power dissipation has been considered to be a bottleneck in realizing LSI compl…

expand abstract