Demystifying 3D ICs: The Pros and Cons of Going Vertical

Davis, W. Rhett; Wilson, John; Mick, S.; Xu, J. Q.; Hao, Hua; Mineo, C.; Sule, Ambarish Mukund; Steer, M.B.; Franzon, Paul D.

doi:10.1109/mdt.2005.136

Cited by 732 publications

(325 citation statements)

References 12 publications

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“…Yet, in a modern microprocessor, the actual generated heat is at the active area of the devices and is caused by the flow of current in these areas leading to the highest temperature in an electronic package (the chip junction temperature). Nonetheless, these results can be very useful for further explorations aimed at implementing these new ultra-thin silicon (substrate) with micro-air channel network in a 3D IC structure 55,56 where another substrate beneath heating-up is analogous to the thermal stage used in this experiment.…”

Section: Aip Advances 5 127115 (2015)mentioning

confidence: 94%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

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Section: Aip Advances 5 127115 (2015)mentioning

confidence: 94%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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“…In order to increase the functionality of the microstructures and metamorphose them into operating devices additional doping with optically active [25,26], magnetic [27,28], and biological [29,30] ingredients has been applied. 3D micro-/nanostructures out of electro-conductive materials would enable realization of plasmonic metamaterials [31,32] and creation of 3D complex microcircuits [33,34]. Doping the material with carbon [35], mixing with ionogel [36], conductive polymer [37], subsequent metallization by electroless coating [8], direct fabrication of metals [38], infiltration [39] was employed.…”

Section: Introductionmentioning

confidence: 99%

Microfabrication of 3D metallic interconnects via direct laser writing and chemical metallization

Jonavičius¹,

Rekštytė²,

Malinauskas³

2014

Lith. J. Phys.

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We present a developed method based on direct laser writing (DLW) and chemical metallization (CM) for microfabrication of three-dimensional (3D) metallic structures. Such approach enables manufacturing of free-form electro-conductive interconnects which can be used in integrated electric circuits such as micro-opto-electro-mechanical systems (MOEMS). The proposed technique employing ultrafast high repetition rate lasers enables efficient fabrication of 3D microstructures on dielectric as well as conductive substrates. The produced polymer links out of organic-inorganic composite matrix after CM serve as interconnects of separate metallic contacts; their dimensions are: height 15 μm, width 5 μm, length 35-45 μm, and they could provide 300 nΩm resistivity measured in a macroscopic way. This proves the techniques potential for creating integrated 3D electric circuits at microscale.

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“…In fact, with respect to planar mainstream technologies, 3-D-ICs provide potential performance advances, reducing interconnection delay and ensuring high bandwidth. Moreover, a form factor reduction is achieved thanks to the small chip footprint and the high integration density [3], [4]. 3-D benefits can fit the requirements of the embedded processor market, where emerging parallelization techniques have highlighted the potential of multi core engines [5].…”

Section: Introductionmentioning

confidence: 99%

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Beanato

Giovannini

Cevrero

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Demystifying 3D ICs: The Pros and Cons of Going Vertical

Cited by 732 publications

References 12 publications

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Microfabrication of 3D metallic interconnects via direct laser writing and chemical metallization

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

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