Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform

Abstract

A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26µA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

“…4c). On the receiver side, a transimpedance amplifier (TIA) analog frontend converts and amplifies the received photo-current into a voltage signal, and a pair of double-data-rate (DDR) samplers converts the signal into the digital domain 31 (Fig. 4d).…”

“…4f. The speed of receivers is currently limited by the long on-chip clock distribution network and can be further improved by integrating local clock generators 31 . Thermal tuning controllers and heater drivers are also included in the transceivers, to adjust for microring resonance fluctuations due to temperature and process variations 32 .…”

The Emergence of Silicon Photonics as a Flexible Technology Platform

“…Due to its simplicity and costs effectiveness, it is of the interest to many research groups to demonstrate initial concepts on the codesigning optoelectronic functions, but seriously limits the data rate for commercial devices. In contrast, flipchip-based 3-D integration approach [14], [265]- [268] has become one of the alternative techniques, which can significantly reduce the parasitic effect introduced by the packing and increase the interconnection density. A representative example is the 10-Gb/s transceiver described in [14], in which the electronic design is realized with 40nm CMOS and many 25-μm pitched microsolder bumps are deposited as interconnect between the optics and electronics.…”

“…A representative example is the 10-Gb/s transceiver described in [14], in which the electronic design is realized with 40nm CMOS and many 25-μm pitched microsolder bumps are deposited as interconnect between the optics and electronics. For more advanced integration, through silicon vias (TSVs) or through oxide vias (TOVs) [268] have been introduced into the silicon photonics integration in 2015, where an order of magnitude reduction in parasitic capacitance and two orders of magnitude higher interconnect density have been reported. Meanwhile, during 2015-2016, STMicroelectronics has introduced a design based on the fine pitch copper pillar interconnect while realizing the electronics in 65-nm CMOS or 55-nm BiCMOS technologies [264]- [266].…”

Ultra-Compact CMOS-Compatible Ytterbium Microlaser

“…The CMOS-compatibility of silicon photonics enables low-form-factor and low-cost integrated optical circuits. Due to these advantages silicon photonics is having a large impact on transceiver technology and new applications such as optical interconnects [1,2], sensors [3,4] and quantum computation [5] are on the horizon. The combination of biomedical sciences with silicon photonics offers compact and packaged devices at a low cost for sensing applications where large equipment was previously required.…”