Demonstration of a reliable high-performance and yielding Air gap interconnect process

Yoo, Hye Jin; Balakrishnan, S.; Bielefeld, J.; Harmes, M.; Hiramatsu, Hidenori; King, Sean W.; Kobrinsky, Mauro J.; Krist, B.; Reese, P.; RamachandraRao, V.; Singh, Kanwal Jit; Suri, S. A. K; Ward, C.

doi:10.1109/iitc.2010.5510708

Cited by 17 publications

(8 citation statements)

References 1 publication

(1 reference statement)

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“…Then, the pinch-off point to close the AG becomes higher, resulting in the risk of contact with the trench bottom of the upper metal level. Second, the AG is prohibited beside the upper via [11][12][13][14]. If a part of the via bottom is outside of the metal line because of size and overlay variation, the via hole is connected to the AG cavity.…”

Section: Design Restrictionsmentioning

confidence: 99%

“…The ultimate solution for a low k-value is the exclusion of all materials from the IMD, which is called an air gap (AG). There are two types of AG processes: (1) removal of the sacrificial material via thermal decomposition or chemical treatment [6][7][8][9][10] through the upper dielectric layer and (2) etching back the IMD followed by pinch-off of the next IMD deposition [11][12][13][14][15]. In the latter case, the AG can be formed selectively at the critical path, leaving dielectric materials in other places, which can retain the mechanical strength.…”

Section: Introductionmentioning

confidence: 99%

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Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

2019

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Air-gap (AG) technology on back-end-of-line (BEOL) provides a means to improve performance without area or power degradation. However, the “blind” use of AG based on traditional design methodologies does not provide sufficient performance gain. We developed an AG-aware design methodology to maximize performance gain with minimum cost. The experimental results of the proposed methodology, which was tested using a 10 nm Advanced RISC Machine (ARM) Cortex-A9 quad-core central processing unit (CPU), indicated a performance gain of 6.1–8.4% compared with traditional AG design. The performance gain achieved represents about half of the 10–15% performance improvement under the same power by a process node shrink. A Si process of consecutive double AG layers was developed by overcoming various process challenges, such as AG depth control, Cu/ultra-low-k damage, the hermetic AG liner, and step-height control above the AG. Furthermore, the capacitance was reduced by 17.0%, which satisfied the target goal in the simulation stage for the assumed structure. The optimized integration process was validated according to the function yield of the CPU, which was comparable to that of a non-AG process. The time-dependent dielectric breakdown and electromigration lifetime of the AG wire satisfied the 10-year criteria, and the assembly yield was verified.

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Section: Design Restrictionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

2019

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“…3, copper traces and vias present in the ULK layers are not modeled in this simulation. The total strain energy release rate G is calculated using equation (2) for both the crack tips and is plotted as shown in Fig. 5.…”

Section: Strain Energy Release Ratementioning

confidence: 99%

“…The 2011 international technology roadmap for semiconductors (ITRS) predicts that the effective dielectric constant (k) of the interlayer dielectrics (ILDs) would scale down linearly in coming years and reach 2.15-2.46 by 2020. Proposed fabrication solutions to reduce k include introduction of air pockets in the dielectric layers by non-conformal deposition [2] or removal of sacrificial materials after multi-level interconnects [3], [4]. However, reduction of k results in reduction of the mechanical strength of these layers [5], [6].…”

mentioning

confidence: 99%

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

Raghavan

Schmadlak²,

Leal³

et al. 2014

IEEE Trans. Device Mater. Relib.

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To meet the electrical performance requirements, copper traces with ultralow-k (ULK) interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed "global" model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a "local model," which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.Index Terms-Back end of line (BEOL) stack reliability, finite-element modeling, flip-chip devices, focused ion beam (FIB), fracture mechanics simulation, lead-free solder reflow, low-k dielectric thin films, microelectronic packaging, porous low-k dielectric, thin film delamination, ultra low-k dielectric cracking.

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“…Accordingly, the date forecasted by the International Technology Roadmap for Semiconductors (ITRS) for insertion of k < 2.5 materials into to high volume interconnect manufacturing has been pushed back several years in a row. 24 These difficulties have driven some corporations to consider more complex and/or expensive means for reducing capacitance such as pore stuffing / filling 25 and selective formation of air-gaps between metal lines 26 .…”

Section: Introductionmentioning

confidence: 99%

Advances in metrology for the determination of Young's modulus for low-k dielectric thin films

et al. 2012

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As the semiconductor nano-electronics industry progresses toward incorporating increasingly lower dielectric constant materials as the inter layer dielectric (ILD) in Cu interconnect structures, thermo-mechanical reliability is becoming an increasing concern due to the inherent fragility of these materials. Therefore, the need for metrologies to assess the mechanical properties and elastic constants of low-k dielectric materials is great. Unfortunately, traditional techniques such as nano-indentation are being increasingly challenged as target low-k ILD thicknesses decrease below 100 nm for sub 16 nm technologies. In this light, we demonstrate the applicability of two new techniques, Brillouin Light Scattering and Contact Resonance Atomic Force Microscopy, for the determination of Young's modulus for low-k dielectric thin films. We show that these techniques yield values that are in agreement with standard nano-indentation measurements and are capable at film thickness on the order of 100 nm or less.

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Demonstration of a reliable high-performance and yielding Air gap interconnect process

Cited by 17 publications

References 1 publication

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

Advances in metrology for the determination of Young's modulus for low-k dielectric thin films

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Demonstration of a reliable high-performance and yielding Air gap interconnect process

Cited by 17 publications

References 1 publication

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Study of Chip&#x2013;Package Interaction Parameters on Interlayer Dielectric Crack Propagation

Advances in metrology for the determination of Young's modulus for low-k dielectric thin films

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Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation