Delta DICE: A Double Node Upset resilient latch

Abstract

In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta interconnection topology, providing enough redundant nodes to guarantee resilience to conventional SNUs, as well as DNUs due to charge sharing. Simulation results demonstrated that in terms of power dissipation and propagation delay, the Delta DICE latch outperforms BISER-based latches that are SNU or DNU tolerant and provides DNU resilience at a small energy×delay penalty compared to other SNU tolerant cells.

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

“…Radiation hardening by design (RHBD) is one of the most effective techniques to mitigate soft errors. In the last decade, researchers have mostly focused on the radiation hardening for memory cells [4,5], flip-flops [6,7] and latches [1,[8][9][10][11][12][13][14][15][16][17][18][19][20][21] using RHBD techniques like multiplemodular redundancy, temporal redundancy, and so on. This paper mainly focuses on these latch designs.…”

“…This paper mainly focuses on these latch designs. In these latch designs, some are only SNU-hardened [8][9][10][11][12][13][14][15] and some are simultaneously hardened for both SNU and DNU [16][17][18][19][20][21]. As far as we know, there is currently only one design that is simultaneously hardened for SNU, DNU and TNU [1].…”

“…Some are completely SNU self-recoverable, such as the designs referred as HLR-CG1/CG2 in [11] and the self-Recoverable, Frequency-aware and Cost-effective (RFC) design in [15]. Among these DNU-hardened latch designs, some are only partially DNU-hardened [16] and some are completely DNU-hardened [17][18][19][20][21], in which the designs in [18][19][20][21] are completely DNU self-recoverable. As for currently the only one design in [1] that completely tolerates any TNU, there are some problems, such as not being completely DNU self-recoverable and having high cost penalties.…”

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

“…Well isolation, guard rings and layout techniques were utilized to solve the multiple upsets caused by charge sharing, but benefits of these techniques are quite limited [9,10]. In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17]. The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance.…”

“…However, the latch in [14] was not fully SEDU tolerant in the circuit design level, and further, layout technique was used to harden the latch. The Delta DICE in [15], DONUT (Double Node Upset Tolerant) in [16], and DNURL (Double-Node-Upset-Resilient Latch) in [17] were derived by the applications of feedback loop. However, it is worth noticing that these latches were carried out with large cost penalties in terms of delay, power consumption and area.…”