Defect-creation effects on abnormal on-current under drain bias illumination stress in a-IGZO thin-film transistors

Ha, Tae-Kyoung; Kim, Yongjo; Cho, Yong-Jung; Kang, Yun-Seong; Yu, SangHee; Kim, GwangTae; Jeong, Hyemin; Park, Jeong Ki; Kim, Ohyun

doi:10.1016/j.sse.2019.107752

Cited by 9 publications

(4 citation statements)

References 28 publications

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“…An extremely low SS indicates that defects in the active layer and interface between the active layer and GI were minimized by the GI deposition temperature after high-temperature annealing. , In addition, μ FE gradually increased from 17.2 to 27.6 cm 2 /Vs with increasing GI deposition temperatures. Several researchers have reported that the increase in μ FE and on-current ( I on ) is closely related to the tail state of the conduction band . As shown in Figure b, the subgap states near the CBM, which may reflect the conduction band tail state, decreased with increasing GI deposition temperature.…”

Section: Resultsmentioning

confidence: 87%

“…Several researchers have reported that the increase in μ FE and on-current (I on ) is closely related to the tail state of the conduction band. 52 As shown in Figure 6b, the subgap states near the CBM, which may reflect the conduction band tail state, decreased with increasing GI deposition temperature. Considering that the conduction band tail states are generally associated with the intercalation of cation disorder, the suppressed V O formation with GI deposition temperature may positively affect the decrease in the conduction band tail state, leading to an increase in μ FE .…”

Section: Evaluation Of Highly Stable and Uniform A-igzo Tftmentioning

confidence: 84%

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Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Kim

Lee

et al. 2023

ACS Appl. Mater. Interfaces

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Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (V TH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a V TH shift of −0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

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Section: Resultsmentioning

confidence: 87%

Section: Evaluation Of Highly Stable and Uniform A-igzo Tftmentioning

confidence: 84%

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Kim

Lee

et al. 2023

ACS Appl. Mater. Interfaces

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“…The TFT not only undergoes a physical change around 22 V V GS but also the on current (I on ) reduces significantly afterwards. Initially, it was thought that the high drain voltage generates hot carriers that rupture the weak oxygen bonds and create acceptor like tail states 19 that limits the I on . Later, thorough investigations confirm that the fabricated IGZO TFTs are stable and operational at high voltage (Figure 12).…”

Section: Integration With Self‐aligned Indium–galium–zinc–oxide Tftsmentioning

confidence: 99%

High‐performance MEMS shutter display with metal‐oxide thin‐film transistors and optimized MEMS element

et al. 2023

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Active matrix prestressed microelectromechanical shutter displays enable outstanding optical properties as well as robust operating performance. The microelectromechanical systems (MEMS) shutter elements have been optimized for higher light outcoupling efficiency with lower operation voltage and higher pixel density. The MEMS elements have been co‐fabricated with self‐aligned metal‐oxide thin‐film transistors (TFTs). Several optimizations were required to integrate MEMS process without hampering the performance of both elements. The optimized display process requires only seven photolithographic masks with ensuring proper compatibility between MEMS shutter and metal‐oxide TFT process.

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“…Thus, these results confirm that the model can accurately predict the I-V characteristics for a-IGZO TFTs with various distributions of DOSs. In addition, it has been reported that new trap states are generated for a-IGZO TFTs under PBS and light stress, which cause the diminishment in electrical performance [10,22,23]. Therefore, in the following, the newly created defect DOS model is used to describe the electrical stability of a-IGZO TFTs under external stress conditions.…”

Section: Model Verificationmentioning

confidence: 99%

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

et al. 2023

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In this work, an electrical stability model based on surface potential is presented for amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) under positive-gate-bias stress (PBS) and light stress. In this model, the sub-gap density of states (DOSs) are depicted by exponential band tails and Gaussian deep states within the band gap of a-IGZO. Meanwhile, the surface potential solution is developed with the stretched exponential distribution relationship between the created defects and PBS time, and the Boltzmann distribution relationship between the generated traps and incident photon energy, respectively. The proposed model is verified using both the calculation results and experimental data of a-IGZO TFTs with various distribution of DOSs, and a consistent and accurate expression of the evolution of transfer curves is achieved under PBS and light illumination.

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Defect-creation effects on abnormal on-current under drain bias illumination stress in a-IGZO thin-film transistors

Cited by 9 publications

References 28 publications

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

High‐performance MEMS shutter display with metal‐oxide thin‐film transistors and optimized MEMS element

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

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