Defect-Aware Design Paradigm for Reconfigurable Architectures

Jain, Rahul; Mukherjee, Atin; Paul, Kolin

doi:10.1109/isvlsi.2006.32

Cited by 20 publications

(5 citation statements)

References 9 publications

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“…First is software based approach where the fault map is given as input to place and route tool and the generated configuration does not use the cells which are faulty [9,10]. Another approach is a hardware based approach, in which the configuration bitstream generated by software is modified by hardware.…”

Section: Motivationmentioning

confidence: 99%

Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

Kalita¹,

Bhattacharyya

Kar

2007

15th International Conference on Advanced Computing and Communications (ADCOM 2007)

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With the increase in complexity of fabrication techniques, yield of the chip production decreases at deep sub-micron technologies. In future fault tolerant techniques will be important to increase the yield of the VLSI chips in advanced fabrication technologies. In regular structure like FPGA, redundancy is commonly used for fault tolerance. Most of the techniques found so far in literature talk about software based changes in the configuration data. In this work we present a solution in which configuration bit stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant columns for replacing faulty cells. Experiments on different circuits using VPR tool shows that there is an average 2.6% increase in the critical path delay while no increase in the area per cell due to our approach.

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Section: Motivationmentioning

confidence: 99%

Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

Kalita¹,

Bhattacharyya

Kar

2007

15th International Conference on Advanced Computing and Communications (ADCOM 2007)

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“…As manufacturing yield decreases, one of the future challenges is to find a way to use a maximum of manufactured circuits tolerating physical defects all over the chip [1] [2]. Compared to ASICs, FPGAs have attained a central focus due to their ability to integrate more complex applications, their flexibility and good performance.…”

Section: Introductionmentioning

confidence: 99%

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA

Blanchardon

Chotin-Avot

Mehrez

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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Abstract-As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add redundancy to propose defect-tolerant architectures. But, hardware redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAMbased Mesh of Clusters FPGA and different strategies to locally insert hardware redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic hardware redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).

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“…Specifically, in literature, there are two mainstream approaches for designing fault-tolerant systems. The first deals with the design of new hardware elements that are fault-tolerant enabled [Nikolic et al 2002;Kastensmidt et al 2006;Yu and Lemieux 2005;Campregher et al 2005], whereas the desired fault masking in the second approach is provided at software level with the usage of specialized CAD tools [Bhaduri and Shukla 2004;Xilinx 2011d;Jain et al 2006;Doumar et al 1999;Koren and Krishna 2007].…”

Section: Introductionmentioning

confidence: 99%

“…Since this approach does not impose any hardware modifications, it is widely accepted for research and product development. Among others, algorithms that provide application P&R under fault-tolerant [Jain et al 2006;Doumar et al 1999] and/or reliability [Sivaswamy and Bazargan 2008] constraints have been proposed, whereas a solution that embeds testing operations and alternative configurations into bitstream files is discussed in Rubin and DeHon [2009]. Also, there are solutions that perform application P&R by taking into consideration a defect map of the target FPGA in order to avoid utilizing nonfunctional hardware resources (either routing or logic blocks).…”

Section: Introductionmentioning

confidence: 99%

A Framework for Supporting Adaptive Fault-Tolerant Solutions

Siozios

Soudris

Hübner

2014

ACM Trans. Embed. Comput. Syst.

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For decades, computer architects pursued one primary goal: performance. The ever-faster transistors provided by Moore's law were translated into remarkable gains in operation frequency and power consumption. However, the device-level size and architecture complexity impose several new challenges, including a decrease in dependability level due to physical failures. In this article we propose a software-supported methodology based on game theory for adapting the aggressiveness of fault tolerance at runtime. Experimental results prove the efficiency of our solution since it achieves comparable fault masking to relevant solutions, but with significantly lower mitigation cost. More specifically, our framework speeds up the identification of suspicious failure resources on average by 76% as compared to the HotSpot tool. Similarly, the introduced solution leads to average Power×Delay (PDP) savings against an existing TMR approach by 53%. ACM Reference Format:Kostas Siozios, Dimitrios Soudris, and Michael Hübner. 2014. A framework for supporting adaptive fault tolerant solutions.

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Defect-Aware Design Paradigm for Reconfigurable Architectures

Cited by 20 publications

References 9 publications

Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA

A Framework for Supporting Adaptive Fault-Tolerant Solutions

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