Deep Level Study of VPE Layers for GaAs FET Devices

Abstract

An AsC1JH2/GaAs solid source VPE system has been developed to grow device quality epi layers. The traps found by optical deep level capacitance transient spectroscopy in the epi layers grown in this system are one electron trap, identified as EL2, and three hole traps near the active layer and buffer layer interface 9 The hole traps were found to be impurity or GaAs intrinsic defect related. The solid GaAs source was found to be the source of impurity contamination. The intrinsic deep trap is influenced by the change in the As/Ga ratio in the gas phase. Low etch flow rate is found to minimize both the impurity transport from solid GaAs source and the intrinsic defect density.