Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Bayraktaroglu, I.; Orailoğlu, Alex

doi:10.1109/vtest.2003.1197641

Cited by 46 publications

(47 citation statements)

References 22 publications

(32 reference statements)

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“…Another technique [4] uses a dynamically reconfigurable scan tree that applies a part of the test sequence in scan tree mode and the other part in single scan mode. Reference [5] describes a decompression hardware scheme for test pattern compression. References [5] and [6] use compression algorithms with concurrent application of compaction and compression.…”

mentioning

confidence: 99%

Dynamic scan clock control in BIST circuits

Shanmugasundaram

Agrawal

2011

2011 IEEE 43rd Southeastern Symposium on System Theory

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Abstract-We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented as on-chip hardware. Two models, one for test sets with peak activity factor of 1 and the other for test sets with peak activity factor lower than 1 have been proposed. In test sets with peak activity factors of 1, the test time reduction accomplished depends upon an average activity factor of αin. For low αin, about 50% test time reduction is analytically shown. With moderate activity, αin = 0.5, simulated test data gives about 25% test time reduction for ITC02 benchmarks. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead. In test sets with peak activity factors lower than 1, the test time reduction depends on an input activity factor of αin and an output activity factor of αout. For low αin and high αout, a test time reduction of about 50% is analytically shown.

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confidence: 99%

Dynamic scan clock control in BIST circuits

Shanmugasundaram

Agrawal

2011

2011 IEEE 43rd Southeastern Symposium on System Theory

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“…The parameter c is determined based on the compatibilities and the logic dependencies between the scan chains for different test cubes. The concept of scan chain compatibility and the associated fan-out structure have been utilized in a number of papers [1,7] since the broadcast scan architecture was presented in [12]. In addition to the compatibilities between the scan chains, we also exploit the logic dependencies between the scan chains to reduce c.…”

Section: A Width Compressionmentioning

confidence: 99%

“…Let b k,i,j denote the jth data bit that is shifted to the ith input of the fan-out structure for the kth test pattern. The ith input is logically dependent on a set of inputs {u 1 …”

Section: A Width Compressionmentioning

confidence: 99%

“…It is easy to show that if a fault is detectable in the original circuit with m external channels, it is also detectable in the circuit with c external channels obtained after width compression. In contrast to [1], no attempt is made here to make c any smaller by relaxing care bits or by interleaving width compression with test generation.…”

Section: A Width Compressionmentioning

confidence: 99%

“…A number of related techniques for two-dimensional compression based on test cubes rely on the interleaving of the width and height compression procedures [1]. Such methods require tailored test development solutions that can support incremented test generation as the compression circuit is determined; thus even though these methods are non-intrusive in term of circuit redesign, they require structural information about the circuit under test.…”

Section: Introductionmentioning

confidence: 99%

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Efficient space/time compression to reduce test data volume and testing time for IP cores

Chakrabarty

Kajihara

et al.

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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Abstract-We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

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