DAG-aware AIG rewriting a fresh look at combinational logic synthesis

Mishchenko, Alan; Chatterjee, Saurav; Brayton, Robert K.

doi:10.1145/1146909.1147048

Cited by 318 publications

(232 citation statements)

References 22 publications

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“…Such circuit representations are typically afterwards automatically translated (encoded) into CNF for applying a CNF-level SAT solver to determine satisfiability of the formula. Various simplification techniques and intricate CNF encoders for general propositional formulas and especially circuit-level SAT instance representations have been proposed; see [43,8,28,41,20,40,13] for examples.…”

Section: Introductionmentioning

confidence: 99%

Simulating Circuit-Level Simplifications on CNF

2011

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Boolean satisfiability (SAT) and its extensions have become a core technology in many application domains, such as planning and formal verification, and continue finding various new application domains today. The SAT-based approach divides into three steps: encoding, preprocessing, and search. It is often argued that by encoding arbitrary Boolean formulas in conjunctive normal form (CNF), structural properties of the original problem are not reflected in the CNF. This should result in the fact that CNF-level preprocessing and SAT solver techniques have an inherent disadvantage compared to related techniques applicable on the level of more structural SAT instance representations such as Boolean circuits. Motivated by this, various simplification techniques and intricate CNF encodings for circuit-level SAT instance representations have been proposed. On the other hand, based on the highly efficient CNF-level clause learning SAT solvers, there is also strong support for the claim that CNF is sufficient as an input format for SAT solvers.In this work we study the effect of CNF-level simplification techniques, focusing on SatElite-style variable elimination (VE) and what we call blocked clause elimination (BCE). We show that BCE is surprisingly effective both in theory and in practice on CNF formulas resulting from a standard CNF encoding for circuits: without explicit knowledge of the underlying circuit structure, it achieves the same level of simplification as a combination of circuit-level simplifications and previously suggested polarity-based CNF encodings. We also show that VE can achieve many of the same effects as BCE, but not all. On the other hand, it turns out that VE and BCE are indeed partially orthogonal techniques. We also study 2 the practical effects of combining BCE and VE for reducing the size of formulas and on the running times of state-of-the-art SAT solvers. Furthermore, we address the problem of how to construct original witnesses to satisfiable CNF formulas when applying a combination of BCE and VE.

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Section: Introductionmentioning

confidence: 99%

Simulating Circuit-Level Simplifications on CNF

2011

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“…There has been a growing interest in AIGs as a functional representation for a variety of tasks in Electronic Design Automation (EDA) such as logic synthesis, technology mapping, verification, and equivalence checking [6,10,20,21,28]. Especially, the recent emergence of efficient boolean satisfiability (SAT) solvers that use AIGs instead of the Binary Decision Diagrams (BDD) has made AIGs popular in EDA.…”

Section: And-inverter Graph (Aig)mentioning

confidence: 99%

“…AIG is an efficient representation for manipulation of boolean functions. It is increasingly used in logic synthesis, technology mapping, verification, and boolean satisfiability checking [6,10,20,21,28]. However, to the best of our knowledge, our work is the first GPU based electronic design automation solution using AIGs.…”

Section: Introductionmentioning

confidence: 99%

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Şen

Akşanlı

Bozkurt

2011

Int J Parallel Prog

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Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

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“…2. The use of AIGs eases the implementation of many useful logic synthesis transformations (e.g., [10,11]). …”

Section: The Abc Synthesis Frameworkmentioning

confidence: 99%

Improving logic density through synthesis-inspired architecture

Anderson

Wang

2009

2009 International Conference on Field Programmable Logic and Applications

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We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14% more LUTs and have 12% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 2.5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

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DAG-aware AIG rewriting a fresh look at combinational logic synthesis

Cited by 318 publications

References 22 publications

Simulating Circuit-Level Simplifications on CNF

Simulating Circuit-Level Simplifications on CNF

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Improving logic density through synthesis-inspired architecture

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