Current loadability of ICA for flip chip applications

Haberland, Julian; Pahl, B.; Schmitz, Stefan; Kallmayer, Christine; Aschenbrenner, R.; Reichl, H.

doi:10.1109/eptc.2002.1185657

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…The latter could inhibit its use when thin Si bare dies and metallic layers on soft polymeric substrates (e.g. inkjet-printed, sputtered tracks) are to be interconnected, due to their high fragility [29], and could additionally induce deformation on low rigidity polymeric substrates. Additionally, relatively high coplanarity between the bare die and the substrate is needed to prevent reliability problems [32], especially when using ball bonding bumps.…”

Section: Methodsmentioning

confidence: 99%

“…Additionally, relatively high coplanarity between the bare die and the substrate is needed to prevent reliability problems [32], especially when using ball bonding bumps. The dimensions and form factor of the bumps can alter the coplanarity which in turn can create differences in bonding pressures at each pad, including cracks in the chips [29]. Furthermore, its deposition requires the precise optimization of the amount of paste and mask design, in order to avoid overflowing onto sensitive areas, such as chemical sensors [58].…”

Section: Methodsmentioning

confidence: 99%

“…Besides ICA, anisotropic conductive adhesives (ACAs) in film [22][23][24] and paste [25][26][27][28] formats have been employed to integrate high-resolution interconnections. However, such methods are developed and optimized for rigid/rigid assemblies, requiring relatively high pressure to entrap and deform the particles between the interconnection pads, which could induce cracks on thin Si bare dies [29]. Particle deformation is lower when using polymeric substrates [30] due to their flexible nature, which in turn increases the interconnection resistance [31].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Quintero¹,

Briand²,

Rooij³

2015

J. Micromech. Microeng.

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In this paper, a low temperature flip-chip integration technique for Si bare dies is demonstrated on flexible PET substrates with screen-printed circuits. The proposed technique is based on patterned blind vias in dry film photoresist (DP) filled with isotropic conductive adhesive (ICA). The DP material serves to define the vias, to confine the ICA paste (80 µm-wide and potentially 25 µm-wide vias), as an adhesion layer to improve the mechanical robustness of the assembly, and to protect additional circuitry on the substrate. The technique is demonstrated using gold-bumped daisy chain chips (DCCs), with electrical vias resistances in the order to hundreds of milliohms, and peel/shear adhesion strengths of 0.7 N mm−1 and 3.2 MPa, respectively, (i.e. at 1.2 MPa of bonding pressure). Finally, the mechanical robustness to bending forces was optimized through flexural mechanics models by placing the neutral plane at the DCC/DP adhesive interface. The optimization was performed by reducing the Si thickness from 400 to 37 µm, and resulted in highly robust integrated assemblies withstanding 10 000 cycles of dynamic bending at 40 mm of radius, with relative changes in vias resistance lower than 20%. In addition, the electrical vias resistance and adhesion strengths were compared to samples integrated with anisotropic conductive adhesives (ACAs). Besides the low temperature and high integration resolution, the proposed method is compatible with large area fabrication and multilayer architectures on foil.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%