2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis 2010
DOI: 10.1109/sc.2010.15
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Cited by 54 publications
(26 citation statements)
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“…As the number of cores on chip increases and with the ever-growing demands for higher performance, lower power consumption, and better QoS guarantees, various NoC designs and advancements are continuously proposed. For example, several works have presented approaches to dynamically manage and reduce the network's power consumption [Jafri et al 2012;Mishra et al 2010;Kim et al 2011]. Others have proposed alternative scheduling [Stuijk et al 2006], resource reservation methods , and arbitration schemes that achieve better QoS or provide QoS bounds for certain types of traffic [Al Faruque et al 2006].…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…As the number of cores on chip increases and with the ever-growing demands for higher performance, lower power consumption, and better QoS guarantees, various NoC designs and advancements are continuously proposed. For example, several works have presented approaches to dynamically manage and reduce the network's power consumption [Jafri et al 2012;Mishra et al 2010;Kim et al 2011]. Others have proposed alternative scheduling [Stuijk et al 2006], resource reservation methods , and arbitration schemes that achieve better QoS or provide QoS bounds for certain types of traffic [Al Faruque et al 2006].…”
Section: Related Workmentioning
confidence: 99%
“…Routers often incorporate advanced features such as speculation, escape channels, and aggressive and prioritized allocation schemes [Al Faruque et al 2006]. Power constraints drive designs towards dynamic power management as well as adaptive resource and network reconfiguration [Jafri et al 2012;Mishra et al 2010;Kim et al 2011]. Irregular topologies, adaptive routing algorithms, and dynamic resource allocation are some of the solutions proposed to adapt network characteristics to application demands [Krishna et al 2011] .…”
Section: Introductionmentioning
confidence: 99%
“…Sartori et al [39] discuss to use hierarchical structure to cap the power of many-core systems. Another related piece of work by Mishra et al [30,29] uses absolute BIPS to allocate the chip power budget to each power island and performs per-island power control. However, these solutions assume the independence of workloads among all the cores.…”
Section: Related Workmentioning
confidence: 99%
“…Although a few recent studies [47,39,29] present scalable control algorithms for manycore architectures based on per-core DVFS, they do not consider multi-threaded parallel applications and assume that the workload of every core is independent. As a result, these solutions may unnecessarily decrease the DVFS levels of the CPU cores running the critical threads in barrier-based multi-threaded applications.…”
Section: Introductionmentioning
confidence: 99%
“…However, suitable controls must be in place to prevent a processor from exceeding the power dissipation target in the unlikely event of a workload spike that would increase the power dissipation beyond this design target leading to disruptive failures. Consequently, to improve the cost-effectiveness of the systems several on-line control techniques have emerged that adjust system parameters to limit power consumption [2], [3], [4] (see also references therein). These techniques are based on dynamic scaling of the voltage and/or clock frequency for controlling the power dissipated by a processor in order to limit it to a certain value called the power cap.…”
Section: Introductionmentioning
confidence: 99%