Counter-Based Cache Replacement and Bypassing Algorithms

Kharbutli, Mazen; Solihin, Yan

doi:10.1109/tc.2007.70816

Cited by 179 publications

(128 citation statements)

References 25 publications

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“…In [1], Kharbutli et al relaxed cache inclusion and bypassed data from L2 (LLC) only, requiring less hardware overhead. Similarly focused on LLC, [9] creates new replacement policy on last-level shared cache (L2) by adding two tables and counter.…”

Section: Related Workmentioning

confidence: 99%

“…The memory system, especially shared last-level cache (LLC), is impacted by these accesses; different types of concurrent workloads result in lower hit rate or even thrashing when the working set is larger than the cache size. In order to better manage limited cache space, selectively bypassing data from the LLC has been shown to ameliorate the problem [1,2,3].…”

Section: Introductionmentioning

confidence: 99%

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Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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Bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large data portions are never reused, wasting system resources. This paper proposes an alternative method to predict data bypassing using Support Vector Machine (SVM). Based on access traces obtained from a simulator, SVM is trained to generate bypass models which are integrated into the simulator to quantify LLC performance improvements. Results show that SVM can classify which data to bypass, improving LLC performance, achieving an average 6.72% miss rate decrease across SPLASH2 benchmark combinations.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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show abstract

“…Various other solutions for efficient cache management have been reported in [8]- [10], but they either require significant hardware or drastically change the organization of the existing cache design. A single cache management scheme, with minimal changes to the existing structure and capability to effectively address all of the problems in this field, is highly desirable.…”

Section: Existing Solutionsmentioning

confidence: 99%

Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement

Jin

Yu³

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYTo improve Last-Level Cache (LLC) management, numerous approaches have been proposed requiring additional hardware budget and increased overhead. A number of these approaches even change the organization of the existing cache design. In this letter, we propose Adaptive Insertion and Promotion (AIP) policies based on Least Recently Used (LRU) replacement. AIP dynamically inserts a missed line in the middle of the cache list and promotes a reused line several steps left, realizing the combination of LRU and LFU policies deliberately under a single unified scheme. As a result, it benefits workloads with high locality as well as with many frequently reused lines. Most importantly, AIP requires no additional hardware other than a typical LRU list, thus it can be easily integrated into the existing hardware with minimal changes. Other issues around LLC such as scans, thrashing and dead lines are all explored in our study. Experimental results on the gem5 simulator with SPEC CUP2006 benchmarks indicate that AIP outperforms LRU replacement policy by an average of 5.8% on the misses per thousand instructions metric.

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“…Each tag has 8 bits hashed PC and 1 bit spill bit to represent whether it is spilled block or not. This prediction table style is borrowed from [4].…”

Section: Life Time Predictionmentioning

confidence: 99%

Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors

Eom

Kwak

Jhang

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn Chip Multi-Processors (CMPs), private L2 caches have potential benefits in future CMPs, e.g. small access latency, performance isolation, tile-friendly architecture and simple low bandwidth on-chip interconnect. But the major weakness of private cache is the higher cache miss rate caused by small private cache capacity. To deal with this problem, private caches can share capacity through spilling replaced blocks to other private caches. However, indiscriminate spilling can make capacity problem worse and influence performance negatively. This letter proposes throttling capacity sharing (TCS) for effective capacity sharing in private L2 caches. TCS determines whether to spill a replaced block by predicting reuse possibility, based on life time and reuse time. In our performance evaluation, TCS improves weighted speedup by 48.79%, 6.37% and 5.44% compared to non-spilling, Cooperative Caching with best spill probability (CC) and Dynamic Spill-Receive (DSR), respectively.

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Counter-Based Cache Replacement and Bypassing Algorithms

Cited by 179 publications

References 25 publications

Applying SVM to data bypass prediction in multi core last-level caches

Applying SVM to data bypass prediction in multi core last-level caches

Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement

Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors

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