Convolutional compaction of test responses

Rajski, J.; Tyszer, Jerzy; Wang, Chen; Reddy, S.M.

doi:10.1109/test.2003.1270904

Cited by 121 publications

(71 citation statements)

References 16 publications

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“…A second category of methods achieves compression by compacting unload data and allowing the tester to selectively ignore measures [14], [15]. However, design and fault-independent test-response compaction necessarily results in some loss of data; therefore, aliasing and X-masking can occur.…”

Section: X-tolerant Compression Of Unload Datamentioning

confidence: 99%

Scalable selector architecture for x-tolerant deterministic BIST

Wohl

Waicukauski

Patel

2004

Proceedings of the 41st Annual Design Automation Conference

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X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full Xtolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG.

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Section: X-tolerant Compression Of Unload Datamentioning

confidence: 99%

Scalable selector architecture for x-tolerant deterministic BIST

Wohl

Waicukauski

Patel

2004

Proceedings of the 41st Annual Design Automation Conference

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“…Hence, only part of output responses are sampled for diagnosis or output responses should be compressed by output compaction. Since the volume of output responses for a large SoC (system-on-chip) often exceeds memory capacity of the tester, output compaction is widely used to reduce output test data volume [10,13,12]. Almost all output compression techniques employ lossy compression.…”

Section: Introductionmentioning

confidence: 99%

Machine learning-based volume diagnosis

Wang

Wei

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…The proposed input compression method can be used with recent output compaction methods such as X-compact [2], convolutional compaction [25], and i-compact [26] to further reduce test data volume.…”

Section: Introductionmentioning

confidence: 99%

Test Data Compression Using Selective Encoding of Scan Slices

Wang

Chakrabarty

2008

IEEE Trans. VLSI Syst.

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Abstract-We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To drive scan chains, we use only tester channels, where = log 2 ( +1) +2. In the best case, we can achieve compression by a factor of using only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as Embedded Deterministic Test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.

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Convolutional compaction of test responses

Cited by 121 publications

References 16 publications

Scalable selector architecture for x-tolerant deterministic BIST

Scalable selector architecture for x-tolerant deterministic BIST

Machine learning-based volume diagnosis

Test Data Compression Using Selective Encoding of Scan Slices

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