2012 IEEE International Reliability Physics Symposium (IRPS) 2012
DOI: 10.1109/irps.2012.6241874
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Controlling uniformity of RRAM characteristics through the forming process

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Cited by 55 publications
(46 citation statements)
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“…To confirm the volatility nature at a low operating current of the T3 memory device, we have adopted Agilent V4400 test system to check the LRSs at different I CC s such as 1, 5, 10 and 15 µA respectively. It can be seen that the memory state changed very quickly even at 30 milliseconds after stressing the memory cells at 1-10 µA I CC s. We have also adopted constant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 voltage stress (CVS) method, 46 whereas the memory cells were stressed at 2.3 V for 1500 seconds; nevertheless, the T3 memory device does not show any retention properties (see Figure S3 in the Supporting Information). Although the T3 memory device shows nonvolatility at I CC ~15 µA, the gradual degradation of memory state towards HRS has been observed even after 60 seconds (not shown here).…”
Section: Pre-forming Ultra-low Power Operation the Typical I-v Featumentioning
confidence: 99%
“…To confirm the volatility nature at a low operating current of the T3 memory device, we have adopted Agilent V4400 test system to check the LRSs at different I CC s such as 1, 5, 10 and 15 µA respectively. It can be seen that the memory state changed very quickly even at 30 milliseconds after stressing the memory cells at 1-10 µA I CC s. We have also adopted constant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 voltage stress (CVS) method, 46 whereas the memory cells were stressed at 2.3 V for 1500 seconds; nevertheless, the T3 memory device does not show any retention properties (see Figure S3 in the Supporting Information). Although the T3 memory device shows nonvolatility at I CC ~15 µA, the gradual degradation of memory state towards HRS has been observed even after 60 seconds (not shown here).…”
Section: Pre-forming Ultra-low Power Operation the Typical I-v Featumentioning
confidence: 99%
“…Despite intense efforts, many issues remain. Much of these challenges are discussed in the literature and are attributed to random filament formation and current overshoot during forming [1][2][3].…”
Section: Introductionmentioning
confidence: 99%
“…One of the major factors affecting the filament properties is the forming current compliance limit, which determines the overall resistance of the formed filament. However, the current compliance (as defined by the electrical measurement setup) is hard to practically control because the current during a fast transient forming process may exceed the compliance limit (aka overshoot) due to discharge of the parasitic capacitance upon resistance change [2][3][4][5]. Such overshoot then leads to device-to-device LRS variations, which can be seen as the variations of the maximum RESET current.…”
Section: Introductionmentioning
confidence: 99%
“…Although the switching characteristics have been explained by many theories, the switching mechanisms are still not fully understood, the most problematic step is the electroforming process of these metal oxide resistive switching (RS) materials [3]. Typically this process is executed only one time for a memory array, and stable resistance switching could be realized after this step.…”
Section: Introductionmentioning
confidence: 99%