Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads

Bharti, Pramod Kumar; Jain, Saurabh; Pillai, Kamlesh; Sayyaparaju, Sagar Varma; Kalsi, Gurpreet S.; Mekie, Joycee; Subramoney, Sreenivas

doi:10.1109/iscas48785.2022.9937781

Cited by 3 publications

(1 citation statement)

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“…The DW6T SRAM cells, which are modified from compact 6T foundry bitcells with no area increase, store the signed 4b weights for calculation. Utilization of the dual-wordline structure reduces power consumption and write-disturb issue [24] during the computation process. The inputs for calculation are given in the timing domain, produced by an on-chip simple and robust pulse generator.…”

Section: Introductionmentioning

confidence: 99%

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks

Gu,

Dou,

You

et al. 2024

IEEE Access

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In this paper, we present an analog-mixed-signal 6T SRAM computing-in-memory (CIM) macro. The macro uses dual-wordline 6T bitcells to reduce power consumption and write-disturb issues. The macro also proposes an analog computation logic circuit for high precision, energy efficient charge-domain computation. The bitcell structure combined with the analog computation logic circuit allows direct input of signed activations and weights to the chip for full signed computation. The proposed macro consists of four CIM blocks, each with four 32x8 compute blocks, a pulse generator, an analog computation logic circuit and a SAR-ADC. Fabricated in a 55 nm process, our CIM macro test chip achieves an energy efficiency of 7.3 TOPS/W. A comprehensive computing test that encompasses the entire range of inputs and weights has been conducted. The results show that the CIM macro test chip can achieve a precision of 79.51% in a 1-FE error range of 71.88%. The target application of the proposed CIM macro is lightweight neural networks, this is demonstrated by mapping a pre-trained network into the macro and achieving a recognition accuracy of 92.28% on the CIFAR-10 dataset. The design surpasses existing designs in comprehensive consideration of energy efficiency, technology and bit width. Computing-in-memory, SRAM, dual-wordline, neural network, charge-domain, multiplyand-accumulate INDEX TERMS

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Section: Introductionmentioning

confidence: 99%