Compositional Semantics of System-Level Designs Written in SystemC

Razavi, Niloofar; Sirjani, Marjan

doi:10.1007/978-3-540-75698-9_8

Cited by 2 publications

(4 citation statements)

References 11 publications

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“…In addition, [14,18,19] also lack an efficient verification back-end. Our approach, in contrast, is implemented in an automatic tool.…”

Section: Related Workmentioning

confidence: 96%

“…The works mentioned in [14,18,19,22], although valuable and applicable in many cases, lack a tool to automatically apply the given approaches on SystemC designs and obtaining the given formalisms. In addition, [14,18,19] also lack an efficient verification back-end.…”

Section: Related Workmentioning

confidence: 99%

“…In [18] and [19] the structure of the SystemC designs are captured by a component-based coordination language. In a parallel work with the current paper, a process algebraic semantics is proposed in [11].…”

Section: Related Workmentioning

confidence: 99%

“…Test bench generation is a time consuming task and is not reliable in validation of complex systems. To overcome this problem the tendency is now directing to the development of formal techniques to augment standard SystemC verification [7,15,19,22]. Model checking [6] is a formal verification technique with the purpose of verifying specifications given in temporal logic formulas for concurrent systems.…”

Section: Introductionmentioning

confidence: 99%

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An effective approach for model checking SystemC designs

Behjati

Sabouri

Razavi

et al. 2008

2008 8th International Conference on Application of Concurrency to System Design

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SystemC is a system level modeling language with the goal of enabling verification at higher levels of abstraction. In this paper, we propose a mapping from SystemC designs to Rebeca models supported by an automatic tool, Sytra. Rebeca verification tool set is then available for verifying LTL and CTL properties. The mapping is aimed to preserve the concurrent and event-driven nature of SystemC. This work is part of a project (Sysfier) to formally verify SystemC designs. The applicability of our approach is shown by a set of small and medium sized case studies, and the scalability of the approach is shown by the verification of a single-cycle MIPS design.

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“…In addition, [14,18,19] also lack an efficient verification back-end. Our approach, in contrast, is implemented in an automatic tool.…”

Section: Related Workmentioning

confidence: 96%