Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

Huq, S. M. Ishraqul; Baroi, Oli Lowna; Shihab, Sk. Aqiluzzaman; Biswas, Saroj

doi:10.1109/tcsii.2020.3027897

Cited by 10 publications

(7 citation statements)

References 11 publications

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“…The phase noise is comparable with references [17], [19]. The power dissipation for the architectures given in references [16] is lower because of the lower technology node. In References [17], and [18], ROSCs using inverter d-cells are designed for eight and five stages, 1mW [19] and in References [19], a pseudo-differential ring VCO with a double tuning approach is used in 28nm FD-SOI CMOS technology.…”

Section: Post Layout Simulation Resultssupporting

confidence: 64%

“…A comparison between proposed and published ROSCs is shown in Table II. The phase noise performance of the proposed ring VCO is better than the architectures given in references [16], [18], [20]. The phase noise is comparable with references [17], [19].…”

Section: Post Layout Simulation Resultssupporting

confidence: 49%

supporting

confidence: 69%

“…Output frequency range (control voltage with frequency) is from 0.88 GHz to 2.76 GHz and K V CO is 6.55 GHz V as shown in Fig 8.In addition, Fig.9shows the CSRVCO works fine with variation of process parameter, temperature and supply voltage for control voltage of 1 V.A comparison between proposed and published ROSCs is shown in TableII. The phase noise performance of the proposed ring VCO is better than the architectures given in references[16],[18],[20]. The phase noise is comparable with references[17],[19].…”

supporting

confidence: 51%

“…In the proposed DDC-based CSRVCO, area occupation and power dissipation are comparatively less than ROSC of references [20] and comparable with ROSC of references [17]. FoM is still comparable to ROSCs of references [16]- [20].…”

Section: Post Layout Simulation Resultsmentioning

confidence: 84%

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A Differential Delay Cell for Ring Oscillators

Singh¹,

SINGH²,

Sakare³

2023

Preprint

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<p>This paper presents a differential delay cell (DDC) for a 3-stage current-starved ring voltage-controlled oscillator (CSRVCO). In the proposed delay cell, pass transistors and a pair of back-to-back transistors are connected in a symmetric structure that helps get less jittery output by providing similar charging and discharging paths from the load capacitor. The current flows from similar paths with the same type and number of transistors in the proposed DDC-based CSRVCO. For verifying the DDC operation, the 3-stage CSRVCO using the proposed DDC is implemented with a standard 65nm CMOS technology with 1V supply. Post-layout simulation results confirm the correct operation of the proposed DDC using the CSRVCO with minimal jitter at the output. The proposed CSRVCO can be tuned from 0.88 GHz to 2.76 GHz. The phase noise of -94.54 dBc Hz was measured at 1MHz offset frequency for the center frequency of 2.76 GHz. The CSRVCO was designed using the proposed DDC occupied area 1198.43 μm2, and dissipated power is 5.19mW.</p>

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Section: Post Layout Simulation Resultssupporting

confidence: 64%

Section: Post Layout Simulation Resultssupporting

confidence: 49%

supporting

confidence: 69%

supporting

confidence: 51%

Section: Post Layout Simulation Resultsmentioning

confidence: 84%

See 3 more Smart Citations

A Differential Delay Cell for Ring Oscillators

Singh¹,

SINGH²,

Sakare³

2023

Preprint

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A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

2022

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This paper introduces a current reference based on ∆V GS generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6 V with a line sensitivity equal to 1.2 %/V in the range [0.8-1.8] V and a temperature coefficient equal to 6.3 ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.INDEX TERMS Current reference, low voltage, low power, area-efficient, Internet of Things, sensor nodes, implanted biomedical devices NOMENCLATURE

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