Compact Physical IR-Drop Models for Chip/Package Co-Design of Gigascale Integration (GSI)

Shakeri, K.; Meindl, J.D.

doi:10.1109/ted.2005.848125

Cited by 58 publications

(46 citation statements)

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“…1 care is needed. In this direction, the so-called flip-chips, with an array bonding power distribution network, represented a substantial improvement, and are actually becoming more and more used by chip designers ( [15], [14]). …”

Section: Introduction and Main Resultsmentioning

confidence: 99%

“…One of the simplest such models is the one that appears in the paper by Shakeri and Meindl [15], where the voltage at each point of the integrated circuit surface is modeled in terms of a solution of a Poisson equation with…”

Section: Introduction and Main Resultsmentioning

confidence: 99%

“…Using a combination of analytical and numerical heuristic methods, a formula was found in [15] for the maximum voltage within the SOC (minus the maximum voltage drop). That formula, in the case where L = J 0 = R s = 1, being R s the sheet resistance and J 0 the consumption of current per unit area, reads 1 2π log ε + (0.1511 .…”

Section: Introduction and Main Resultsmentioning

confidence: 99%

“…This expression, is now widely used in the context of chip design. However, the procedure in [15] has a major drawback, and it is the fact that the method is not based on a systematic use of matched asymptotic expansions and thus cannot be easily extended to obtain further terms in the ε-expansion. In principle, although it is not clear from the derivation of the formula in [15], the error in this formula is order ε, which, at a first glance, would seem reasonable for a physical application.…”

Section: Introduction and Main Resultsmentioning

confidence: 99%

“…However, the procedure in [15] has a major drawback, and it is the fact that the method is not based on a systematic use of matched asymptotic expansions and thus cannot be easily extended to obtain further terms in the ε-expansion. In principle, although it is not clear from the derivation of the formula in [15], the error in this formula is order ε, which, at a first glance, would seem reasonable for a physical application. However, as we shall explain in Section 2, the sizes of the pads are not that small in comparison with the size of the whole chip, which justifies the need to calculate a higher order approximation for the voltage drop.…”

Section: Introduction and Main Resultsmentioning

confidence: 99%

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On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

Aguareles

Haro²,

Rius³

et al. 2011

Eur. J. Appl. Math

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Abstract. We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits.In this model the voltage is the solution of a Poisson equation in an infinite planar domain whose boundary is an array of circular pads of radius ε, and we deal with the singular limit ε → 0 case. In comparison with approximations that appear in the electronic engineering literature, our formula is more complete since we have obtained terms up to order ε 15 . A procedure will be presented to compute all the successive terms, which can be interpreted as using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and of the Gauss constant G.

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Section: Introduction and Main Resultsmentioning

confidence: 99%

Section: Introduction and Main Resultsmentioning

confidence: 99%

Section: Introduction and Main Resultsmentioning

confidence: 99%

Section: Introduction and Main Resultsmentioning

confidence: 99%

Section: Introduction and Main Resultsmentioning

confidence: 99%

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