Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability

Guo, Jingrui; Sun, Ying; Wang, Lingfei; Duan, Xinlv; Huang, Kailiang; Wang, Zhaogui; Feng, Junxiao; Chen, Qian; Huang, Zhenhua; Xu, Lei; Geng, Di; Jiao, Guangfan; Yin, Shihui; Wang, Zhengbo; Jing, Weiliang; Li, Ling; Liu, Ming

doi:10.1109/vlsitechnologyandcir46769.2022.9830482

Cited by 10 publications

(3 citation statements)

References 3 publications

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“…PBTI in IGZO is mainly due to charge trapping or relaxation kinetics, which have different time kinetics, voltage acceleration factors and activation energies. As reported in [7], [25], a physics-based model is employed to reproduce stress and relaxation traces recorded under various test conditions. Here, we simplify the complex physics-based model to a unified empirical BTI degradation model that can be expressed as…”

Section: X(nm)mentioning

confidence: 99%

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Xu,

Chen,

et al. 2024

IEEE J. Electron Devices Soc.

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Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for longretention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multigate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to ~ 50 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuationresistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

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Section: X(nm)mentioning

confidence: 99%

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Xu,

Chen,

et al. 2024

IEEE J. Electron Devices Soc.

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“…Considerable research and development efforts have been invested in the exploration of thin-film transistors (TFTs), utilizing a diverse array of thin-film materials. Various materials, including metal oxides characterized by low power consumption and minimal leakage [ 1 , 2 , 3 , 4 ], transition metals dichalcogenides (TMDs) exhibiting high stability and tunable bandgap [ 5 , 6 , 7 ], carbon nanotubes (CNTs) with notable conductivity and diverse structures [ 8 , 9 ], and organic semiconductors characterized by biocompatibility and scalability to various device types [ 10 , 11 , 12 , 13 ], have been employed in the construction of electronic devices. These TFTs offer remarkable versatility in terms of substrate compatibility, with applications extending to transparent glass [ 14 , 15 ], banknotes [ 16 , 17 ], paper [ 18 , 19 ], skin [ 20 , 21 ], and flexible plastics [ 22 , 23 , 24 ].…”

Section: Introductionmentioning

confidence: 99%

Split-Gate: Harnessing Gate Modulation Power in Thin-Film Electronics

Lee,

Kim,

Yoo

2024

Micromachines

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With the increase in electronic devices across various applications, there is rising demand for selective carrier control. The split-gate consists of a gate electrode divided into multiple parts, allowing for the independent biasing of electric fields within the device. This configuration enables the potential formation of both p- and n-channels by injecting holes and electrons owing to the presence of the two gate electrodes. Applying voltage to the split-gate allows for the control of the Fermi level and, consequently, the barrier height in the device. This facilitates band bending in unipolar transistors and allows ambipolar transistors to operate as if unipolar. Moreover, the split-gate serves as a revolutionary tool to modulate the contact resistance by controlling the barrier height. This approach enables the precise control of the device by biasing the partial electric field without limitations on materials, making it adaptable for various applications, as reported in various types of research. However, the gap length between gates can affect the injection of the electric field for the precise control of carriers. Hence, the design of the gap length is a critical element for the split-gate structure. The primary investigation in this review is the introduction of split-gate technology applied in various applications by using diverse materials, the methods for forming the split-gate in each device, and the operational mechanisms under applied voltage conditions.

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“…[1][2][3] The emergence of 2T0C memory cells based on In-Ga-Zn-O (IGZO) channel material with extremely low leakage current, back end of line compatibility, high mobility, and good film uniformity provides a promising approach to overcome the aforementioned mismatch challenge and a find suitable 3D integration scheme. 4) As the charge of the 2T0C cell is stored in the gate capacitor, the non-destructive operation of separating read and write and the unique material characteristics of IGZO contribute the desirable properties of low power, long retention time, and highdensity integration. 3,5) However, there is a potential currentsharing issue in the 2T0C DRAM array, as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

Liang,

Yuan,

et al. 2024

Jpn. J. Appl. Phys.

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In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical Channel-All-Around (CAA) structure are investigated by technology computer-aided design (TCAD) simulation. The simulated IDS~VGS curves of IGZO FeFET exists a large on-off ratio of 107 and memory window, proving that ferroelectric hafnium oxide is satisfied for 2T0C transistor design. To solve the potential current sharing problem of 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of ferroelectric hafnium oxide. This solution shows the remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of IGZO-based FeFET on 2T0C DRAM memory cell, but also providing array design guideline for highly reliable 2T0C memory applications.

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Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability

Cited by 10 publications

References 3 publications

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Split-Gate: Harnessing Gate Modulation Power in Thin-Film Electronics

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

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