Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers

Chen, Tzung-Shi; Sheu, Jang‐Ping

doi:10.1109/icpp.1993.56

Cited by 13 publications

(35 citation statements)

References 12 publications

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“…Chen and Sheu [15] minimize interprocessor communication by first dividing the iteration space into blocks without inter-block communication, and then assigning data and iterations to processors. Tim et al [53] propose a general data partitioning heuristic that considers both parallelism and communication cost.…”

Section: Discussion Of Related Workmentioning

confidence: 99%

Optimizing shared cache behavior of chip multiprocessors

Kandemir

Muralidhara

Narayanan

et al. 2009

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

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One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work well in the CMP case as data accesses from multiple cores can create conflicts in the shared cache space. The main contribution of this paper is a compiler directed code restructuring scheme for enhancing locality of shared data in CMPs. The proposed scheme targets the last level shared cache that exist in many commercial CMPs and has two components, namely, allocation, which determines the set of loop iterations assigned to each core, and scheduling, which determines the order in which the iterations assigned to a core are executed. Our scheme restructures the application code such that the different cores operate on shared data blocks at the same time, to the extent allowed by data dependencies. This helps to reduce reuse distances for the shared data and improves onchip cache performance. We evaluated our approach using the Splash-2 and Parsec applications through both simulations and experiments on two commercial multi-core machines. Our experimental evaluation indicates that the proposed data locality optimization scheme improves inter-core conflict misses in the shared cache by 67% on average when both allocation and scheduling are used. Also, the execution time improvements we achieve (29% on average) are very close to the optimal savings that could be achieved using a hypothetical scheme.

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Section: Discussion Of Related Workmentioning

confidence: 99%

Optimizing shared cache behavior of chip multiprocessors

Kandemir

Muralidhara

Narayanan

et al. 2009

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…The data reference to array A is expressed by A exp 1 exp 2 exp n where exp j , 1 ≤ j ≤ n is an integer-valued linear expression possibly involving loop index variables i 1 , i 2 , i l . This data reference can also be expressed by M A I +ō, where M A is defined as an n × l access matrix, I is the iteration vector, andō is an offset (constant vector), an n × 1 column vector [4]. For example, to the reference A i − 1 i + j surrounded by a 2-deep loop nest with index variables i and j, we have the access representation…”

Section: Data Alignment Relationsmentioning

confidence: 99%

“…For example, i j = 0 1 while i j = 1 1 . For general cases of the above transformation derivations, we can refer to reference [4] for details.…”

Section: Skewed Data Partition and Distributionmentioning

confidence: 99%

“…Chen and Sheu [4], Lim et al [13,14], Ramanujam and Sadayappan [16], and Shih, Sheu, and Huang [18] presented approaches to analyze data reference patterns on a program with structures of nested loops so that the parallelized program can be run on a parallel machine in a communication-free manner with some constraints. Furthermore, Lim et al [13,14] tried to maximize parallelism and minimize communication on a scalable parallel machine by using affine transformations when a program cannot be partitioned in a communication-free manner.…”

Section: Introductionmentioning

confidence: 99%

“…Over the last decade, a great number of researchers paid their attention on maximizing parallelism and minimizing communication for a given program executed on a parallel machine [1,4,5,13,14,[16][17][18]21]. Chen and Sheu [4], Lim et al [13,14], Ramanujam and Sadayappan [16], and Shih, Sheu, and Huang [18] presented approaches to analyze data reference patterns on a program with structures of nested loops so that the parallelized program can be run on a parallel machine in a communication-free manner with some constraints.…”

Section: Introductionmentioning

confidence: 99%

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Skewed Data Partition and Alignment Techniques for Compiling Programs on Distributed Memory Multicomputers

Chen

Chang

2000

Lecture Notes in Computer Science

Self Cite

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Abstract. Minimizing data communication over processors is the key to compile programs for distributed memory multicomputers. In this paper, we propose new data partition and alignment techniques for partitioning and aligning data arrays with a program in a way of minimizing communication over processors. We use skewed alignment instead of the dimension-ordered alignment techniques to align data arrays. By developing the skewed scheme, we can solve more complex programs with minimized data communication than that of the dimension-ordered scheme. Finally, we compare the proposed scheme with the dimension-ordered alignment one by experimental results. The experimental results show that our proposed scheme has more opportunities to align data arrays such that data communications over processors can be minimized.

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Run‐time issues in program partitioning on distributed memory systems

Pande

Agrawal

1995

Concurrency: Pract. Exper.

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SUMMARYOur earlier work reported a Threshold Scheduling Method for compile-time mapping of functional parallelism on distributed-memory systems. The work reported in this paper discusses run-time issues in efficiently supporting the functional parallelism with minimal overheads, through a combination of compile-time and run-time ownership analysis.At compile time, the code generation phase determines whether a local copy of a live definition of a variable needed by a task is available on a given processor, through an ownership analysis.In case ownership cannot be resolved at compile time, an appropriate code is generated to perform analysis at run time. The code generation is carried out so that all the processorscarry the same copy of the compiled program with the individual processorkcode being isolated and the universally owned code being replicated on all processors to minimize run-time overheads. The run-time system maintains the static and dynamic ownerships at every processor to avoid communication overhead on ownership information.We demonstrate the approach by incorporating it in the compiler for targeting a parallel functional language, Sisal (streams and iterations in single assignment language), to Intel Touchstone 8 6 0 systems. Several benchmarks demonstrate the viability of the approach.

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Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers

Cited by 13 publications

References 12 publications

Optimizing shared cache behavior of chip multiprocessors

Optimizing shared cache behavior of chip multiprocessors

Skewed Data Partition and Alignment Techniques for Compiling Programs on Distributed Memory Multicomputers

Run‐time issues in program partitioning on distributed memory systems

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