Column-separated compressive sampling scheme for low power CMOS image sensors

Katic, Nikola; Kamal, Mahdad Hosseini; Kilic, Mustafa Sabri; Schmid, Alexandre; Leblebici, Yusuf

doi:10.1109/newcas.2013.6573620

Cited by 13 publications

(6 citation statements)

References 18 publications

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“…The random sequences can easily be generated by linear feedback shift registers (LFSRs), in a way that a completely new measurement matrix is formed in every LFSR clock cycle. An example of the complete circuit that implements the proposed scheme to obtain high frame-rate operation is given in [22].…”

Section: Discussionmentioning

confidence: 99%

Compressive image acquisition in modern CMOS IC design

Katic

Kamal

Schmid

et al. 2013

Circuit Theory & Apps

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SUMMARYCompressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well-established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non-idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs.

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Section: Discussionmentioning

confidence: 99%

Compressive image acquisition in modern CMOS IC design

Katic

Kamal

Schmid

et al. 2013

Circuit Theory & Apps

Self Cite

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“…When M = 50, the area overhead occupied by measurement matrix generator can be evaluated with the flip-flops consumed by the matrix design scheme. The pseudo-random matrix generator proposed in [33,34] respectively consumes 750 and 65 flip-flops. However, ISC-array LDPC code matrix generator only consumes 50 flip-flops.…”

Section: Algorithm Complexity Analysis Of the Proposed Schemementioning

confidence: 99%

Compressive sensing measurement matrix construction based on improved size compatible array LDPC code

Yuan

Song

Sun

et al. 2015

IET Image Processing

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“…Thus, the proposed scheme only requires 50 flip-flops when M is equal to 50, compared with what would have been 750 flip-flops to enable pseudorandom binary sequences (PRBS) with the same run length for the approach described in [7]. With these improvements, the power required for the matrix generation is reduced to 7 % of that in [7]. Sixty-five flip-flops would be necessary to enable PRBS with the same run length for the approach described in [5].…”

Section: Area Consumption Comparisonmentioning

confidence: 99%

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

Yuan

Song

Sun

et al. 2015

Circuits Syst Signal Process

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We construct and implement a compressive sensing measurement matrix based on improved size-compatible (ISC)-array low-density parity-check (LDPC) code. First, we propose an improved measurement matrix from the array LDPC code matrix. The proposed measurement matrix retains suitable quasi-cyclic structures and supports arbitrary code lengths. It also achieves a high perfect recovery percentage compared with a Gaussian random matrix of the same size. Second, we propose a hardware scheme using cycle shift registers to design the compressive sensing measurement matrix generator. This provides simple circuit architecture during the generation of the measurement matrix. According to simulation verifications, the measurement matrix construction method is effective and entails fewer shift registers and a lower area overhead by using a simplified hardware implementation scheme. The compressive sensing measurement matrix generator can generate all of the required elements in Circuits Syst Signal Process the ISC-array LDPC code matrix with an acceptable hardware overhead. Therefore, it can be widely applied to large-scale sparse signal compressive sensing.

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Column-separated compressive sampling scheme for low power CMOS image sensors

Cited by 13 publications

References 18 publications

Compressive image acquisition in modern CMOS IC design

Compressive image acquisition in modern CMOS IC design

Compressive sensing measurement matrix construction based on improved size compatible array LDPC code

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

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