Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures

Orailoğlu, Alex; Karri, Ramesh

doi:10.1109/92.311639

Cited by 38 publications

(36 citation statements)

References 20 publications

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“…Checkpointing in the context of static scheduling has received limited attention [8,19]. The process model in [9] supports the application of checkpoints, while [19] has proposed a high-level synthesis algorithm for ASICs that introduces low overhead checkpoints in a static schedule.…”

Section: Introductionmentioning

confidence: 99%

“…Very few researchers [14,19,20] consider the optimization of implementations to reduce the overheads due to fault-tolerance and, even if optimization is considered, it is very limited and does not include the concurrent usage of several fault-tolerance techniques. Moreover, the application of faulttolerance techniques is considered in isolation, and thus is not considered in relation to other levels of the design process, including mapping, scheduling and bus access optimization.…”

Section: Introductionmentioning

confidence: 99%

“…The process model in [9] supports the application of checkpoints, while [19] has proposed a high-level synthesis algorithm for ASICs that introduces low overhead checkpoints in a static schedule. When re-execution (which can be equated to a single-checkpoint scheme) is used in a distributed system, Kandasamy [14] proposes a list-scheduling technique for building a static schedule that can mask the occurrence of faults, thus making the re-execution transparent.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Synthesis of fault-tolerant embedded systems with checkpointing and replication

Izosimov

Pop

Eles

et al. 2006

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Synthesis of fault-tolerant embedded systems with checkpointing and replication

Izosimov

Pop

Eles

et al. 2006

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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“…Automatic synthesis of self-recovering microarchitectures has been previously addressed. An algorithm that intertwines checkpoint insertion and scheduling to synthesize self-recovering microarchitectures for supporting fault-recovery in hardware was rst presented in [10]. Guerra et.…”

Section: Related Researchmentioning

confidence: 99%

Heterogeneous built-in resiliency of application specific programmable processors

Kim¹,

Karri²,

Potkonjak³

Proceedings of International Conference on Computer Aided Design

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-Using the exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR processor synthesis imposes several unique tasks on the synthesis process: (i) latency determination targeting k-unit fault-tolerance, (ii) application-to-faulty-unit matching and (iii) HBIR scheduling and assignment algorithms. We address each of them and demonstrate the eectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of designs.

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“…The time overhead for re-execution can be reduced with more complex fault tolerance techniques such as rollback recovery with checkpointing [29], [33], [42]. The main principle of this technique is to restore the last non-faulty state of the failing process, i.e., to recover from faults.…”

Section: A Rollback Recovery With Checkpointingmentioning

confidence: 99%

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

Izosimov

Pop

Eles

et al.

Design, Automation and Test in Europe

142

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Abstract-We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

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Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures

Cited by 38 publications

References 20 publications

Synthesis of fault-tolerant embedded systems with checkpointing and replication

Synthesis of fault-tolerant embedded systems with checkpointing and replication

Heterogeneous built-in resiliency of application specific programmable processors

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

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