Cluster assignment of global values for clustered VLIW processors

Abstract

In this paper high-level language (HLL) variables that are alive in a whole HLL function, across multiple scheduling units, are termed as global values. Due to their long live ranges and, hence, large impact on the schedule, the global values require different compiler optimizations than local values, which span across only one scheduling unit. The instruction scheduler for a clustered ILP processor, which is responsible for cluster assignment of operations and variables, faces a difficult problem of assigning global values to clusters. Our study shows that trivial assignments (e.g. mapping all global values into one cluster) may result in a severe cycle count overhead relative to the unicluster of up to 26.3% for a four cluster VLIW machine. This paper presents three advanced algorithms for assigning global values to clusters based on multi-pass scheduling and affinity of variables. Furthermore, we measure performance of these algorithms on optimized multimedia C applications and assess quality of our algorithms by comparing them to a practical higher performance bound derived from a vast random search. Our algorithms reduce the execution time overhead of the best simple algorithm round-robin from 10.5% to 5.9% for the two cluster VLIW machine and from 17.3% to 14.12% for the four cluster VLIW machine.

Inter-cluster communication in VLIW architectures

“…Note, that our performance and energy measurements in subsequent sections are sensitive to the quality of the compiler and the instruction scheduler, in particular. According to comparisons of our schedule quality against a vast random search [Terechko et al 2003b], our results are only few percentage off, relative to the lowest achieved bounds. Further compiler tuning and optimizations for particular ICC models and global values can increase the presented benefits from clustering.…”

“…The guarded decision tree is an acyclic control-flow graph without join points and side entries, which is a more general case than hyper and superblocks. Furthermore, our instruction scheduler employs an advanced intrafunction analysis for cluster assignment of global values described in Terechko et al [2003b]. Inspired byÖzer et al [1998], Janssen [2001], Kailas et al [2001] and Codina et al [2001], we integrated cluster assignment, instruction scheduling, and register allocation in a single phase.…”

“…Instead of the register-hungry broadcast ICC model from Terechko [2003a], we employed the more promising multicast ICC model. Finally, cluster assignment heuristics of global values presented in Terechko et al [2003b] have been extended from the dedicated issue slot machine to extended results, extended operands, copy operations, and multicast ICC models. In general, all the above-mentioned extensions enabled a comprehensive comparison of all the models within the same ISA, compiler optimizations, and hardware template.…”

Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory

“…For data-intensive applications, such as multimedia and DSP applications, the memory access operations account for approximately half of the cycle count [11], so optimizing the memory access is critical for performance improvement. For VS-SPM memory architectures, assigning variables to the appropriate SPMs will significantly reduce the overhead of remote SPM accesses.…”

Global Variable Partition with Virtually Shared Scratch Pad Memory to Minimize Schedule Length

“…For data-intensive applications, such as multimedia and DSP applications, the memory access operations account for approximately half of the cycle count [5], so optimizing the memory access is critical for performance improvement. For VS-SPM memory architectures, assigning variables to the appropriate SPMs will significantly reduce the overhead of remote SPM accesses.…”