Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

Ciampolini, L.; Gupta, Siddharth; Callen, Olivier; Chhabra, Amit; Dipti, Dibya; Haendler, S.; Kumar, Shailesh; Noblet, D.; Malinge, P.; Planes, N.; Turgis, David; Lecocq, Christophe; Azmi, Shamsi

doi:10.1166/jolpe.2012.1176

Cited by 6 publications

(2 citation statements)

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“…In order to enable minimum operating voltage silicon correlation with the static metrics at ultra-low voltage, the standard Quasi-Monte Carlo (QMC) methodology for characterizing the V M IN of a 6T Low-Power bitcell [7] has been applied to the ultra-wide voltage range 10T bitcell. In this work, the V M IN is the lowest voltage for which the 32kb memory will function safely for a yield of 95% and is set by the limiting operation (write or read) worst-case cell in the memory array.…”

Section: B Quasi-monte Carlo Methodologymentioning

confidence: 99%

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Abouzeid

Bienfait

Akyel

et al. 2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.

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Section: B Quasi-monte Carlo Methodologymentioning

confidence: 99%

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Abouzeid

Bienfait

Akyel

et al. 2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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“…Most of the works about SRAM stability use DC metrics like Static Noise Margin and Write Margin [6]- [8], which are unable to describe real-world SRAM arrays working at some GHz. DC analysis of an SRAM bitcell features only two stable states, the first with an internal node being close to Vdd and the other node close to ground, and the second vice versa.…”

Section: Introductionmentioning

confidence: 99%

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

Akyel

Ciampolini

Thomas

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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This work investigates the effects of process variability on the dynamic stability of a 6-Transistor Static Random Access Memory bitcell manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted SiliconOn-Insulator (UTBB-FDSOI) technology node. The study is carried out for two different well architectures: single-well (peculiar to UTBB-FDSOI) and dual-well (like in standard CMOS), through Most-Probable Failure Point tracking methodology coupled with Importance Sampling. Different failure mechanisms appearing under different operating conditions are discussed. We show that the Read-After-Write failure criterion based on multiple Word-Line pulses is the most accurate way to evaluate bitcell failure rate and thus its yield under realistic dynamic conditions. The methodology exposed in this work is applied to demonstrate the superior properties of the single-well architecture.I.

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SRAM Bitcell Functionality Under Body-Bias

Ciampolini

2020

Integrated Circuits and Systems

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Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

Cited by 6 publications

References 0 publications

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

SRAM Bitcell Functionality Under Body-Bias

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