Characterization of the Variable Retention Time in Dynamic Random Access Memory

Kim, Heesang; Oh, Byoungchan; Son, Younghwan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Seongin; Shin, Hyungcheol

doi:10.1109/ted.2011.2160066

Cited by 22 publications

(13 citation statements)

References 12 publications

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“…Previous work has shown that each VRT cell spends an exponentially distributed amount of time in each state [14,31], and that the distribution of time constants for these exponential distributions is itself exponentially distributed [15]. The shape of our observed distributions appear to be consistent with this prior work.…”

Section: Time Between State Changessupporting

confidence: 87%

“…These works established the key properties of VRT: the existence of multiple retention time states in VRT cells and the exponentially-distributed nature of the amount of time spent in each state. Since then, interest in VRT has focused on identifying its physical cause, primarily by measuring circuit-level features such as leakage currents [3,14,15,16,25,27,29]. No recent work we are aware of has evaluated the impact of VRT in modern DRAM devices.…”

Section: Variable Retention Timementioning

confidence: 99%

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An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Time Between State Changessupporting

confidence: 87%

Section: Variable Retention Timementioning

confidence: 99%

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

View full text Add to dashboard Cite

show abstract

“…While DRAM cells have varying retention time [4], the JEDEC standards specify a minimum of 64ms retention time (32ms for high temperature), which means all DRAM rows must be refreshed within this small time period. Let's call this time period as DRAM Retention Time.…”

Section: Dram Refresh: Background and Terminologymentioning

confidence: 99%

A case for Refresh Pausing in DRAM memory systems

Nair

Chou

Qureshi

2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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DRAM cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement.This paper provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well defined points at which it can potentially be Paused to service a pending read request. Leveraging this property, we propose Refresh Pausing, a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices, and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme.

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“…Such schemes can either decommission high refresh pages [Venkatesan et al 2006] or use multirate refresh where high-retention pages (rows) are refreshed infrequently [Kim and Papaefthymiou 2001;Liu et al 2012;Venkatesan et al 2006]. These approaches rely on having retention characteristics of DRAM cells available and that these characteristics do not change.…”

Section: Other Related Workmentioning

confidence: 99%

“…DRAM cells maintain data integrity using refresh operations, a process whereby the data is rewritten to the cell periodically using sense amplifiers. Although DRAM cells have varying retention time [Kim et al 2011], the JEDEC standards specify a minimum of 64ms retention time (32ms for high temperature), which means that all DRAM rows must be refreshed within this small time period. Let's call this time period DRAM Retention Time.…”

Section: Introductionmentioning

confidence: 99%

Refresh pausing in DRAM memory systems

Nair

Chou

Qureshi

2014

ACM Trans. Archit. Code Optim.

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Dynamic Random Access Memory (DRAM) cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement.This article provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well-defined points at which it can potentially be Paused to service a pending read request. Leveraging this property, we propose Refresh Pausing, a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme.

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Characterization of the Variable Retention Time in Dynamic Random Access Memory

Cited by 22 publications

References 12 publications

An experimental study of data retention behavior in modern DRAM devices

An experimental study of data retention behavior in modern DRAM devices

A case for Refresh Pausing in DRAM memory systems

Refresh pausing in DRAM memory systems

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